The Experts below are selected from a list of 7953 Experts worldwide ranked by ideXlab platform
Manoj Sachdev - One of the best experts on this subject based on the ideXlab platform.
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An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 $\mu$ m CMOS
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Mohammad Sharifkhani, Manoj SachdevAbstract:Based on the dynamic criteria for data stability, we introduce segmented virtual grounding architecture with extended read, write Noise Margin to realize a low leakage current, energy efficient SRAM module. The architecture offers subthreshold operation for the entire module, except for the selected segments. In addition, a new operational mode for the SRAM cell is introduced which allows only the bitlines of the selected columns to be discharged in an operation. The stability of the cells is enhanced in both read and write operation by controlling the cell access time and cell supply voltage, respectively. A 2048 times 20 bit eSRAM unit is implemented in a regular 0.13 mum CMOS technology to confirm the idea. The unit operates at 100 MHz and consumes less than 1 mW in both read and write operations. Thanks to the reverse body bias of the transistors, the leakage current of a 0.4 V cell drops to 27 pA during the non-access time. The measurement results shows a 28% Noise Margin enhancement for this scheme when a subthreshold cell is accessed.
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an energy efficient 40 kb sram module with extended read write Noise Margin in 0 13 mu m cmos
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Mohammad Sharifkhani, Manoj SachdevAbstract:Based on the dynamic criteria for data stability, we introduce segmented virtual grounding architecture with extended read, write Noise Margin to realize a low leakage current, energy efficient SRAM module. The architecture offers subthreshold operation for the entire module, except for the selected segments. In addition, a new operational mode for the SRAM cell is introduced which allows only the bitlines of the selected columns to be discharged in an operation. The stability of the cells is enhanced in both read and write operation by controlling the cell access time and cell supply voltage, respectively. A 2048 times 20 bit eSRAM unit is implemented in a regular 0.13 mum CMOS technology to confirm the idea. The unit operates at 100 MHz and consumes less than 1 mW in both read and write operations. Thanks to the reverse body bias of the transistors, the leakage current of a 0.4 V cell drops to 27 pA during the non-access time. The measurement results shows a 28% Noise Margin enhancement for this scheme when a subthreshold cell is accessed.
Valerio Vignoli - One of the best experts on this subject based on the ideXlab platform.
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power delay area Noise Margin tradeoffs in positive feedback mos current mode logic
IEEE Transactions on Circuits and Systems I-regular Papers, 2007Co-Authors: Massimo Alioto, L Pancioni, S Rocchi, Valerio VignoliAbstract:In this paper, positive feedback source-coupled logic (PFSCL) gates are analyzed from a design point of view. The design space is explored through analytical relationships which relate the gate delay, power consumption and Noise Margin, which are modeled through a simplified circuit analysis. To be more specific, a simple and accurate model of the Noise Margin is used to derive a systematic design strategy to size the transistors' aspect ratios ensuring an assigned Noise Margin for a given bias current. From the knowledge of the transistor sizes, the gate delay is then expressed as a function of the bias current and the supply voltage, both of which define the static power consumption of PFSCL gates, as well as of the logic swing, which determines the Noise Margin. Therefore, this delay model simply relates the speed performance, the power consumption and the Noise Margin of PFSCL gates, and accounts for the dependence on the fan-in and fan-out. Extensive SPICE simulations with a 0.18-m CMOS process confirm the adequate accuracy of the analytical models and the validity of the approximations introduced to simplify the analysis, and a practical design example of an equality comparator is also presented. In order to derive clear guidelines to manage the delay-power-Noise Margin tradeoff, PFSCL gates are analyzed in typical design cases (i.e., design for high speed, low power and power efficiency). For the sake of completeness, the effect of each design parameter on the silicon area occupied by a PFSCL gate is also qualitatively analyzed. The resulting criteria are thus useful to design PFSCL gates without resorting to time-consuming design iterations with a trial and error approach based on simulations.
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Power–Delay–Area–Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic
IEEE Transactions on Circuits and Systems I-regular Papers, 2007Co-Authors: Massimo Alioto, L Pancioni, S Rocchi, Valerio VignoliAbstract:In this paper, positive feedback source-coupled logic (PFSCL) gates are analyzed from a design point of view. The design space is explored through analytical relationships which relate the gate delay, power consumption and Noise Margin, which are modeled through a simplified circuit analysis. To be more specific, a simple and accurate model of the Noise Margin is used to derive a systematic design strategy to size the transistors' aspect ratios ensuring an assigned Noise Margin for a given bias current. From the knowledge of the transistor sizes, the gate delay is then expressed as a function of the bias current and the supply voltage, both of which define the static power consumption of PFSCL gates, as well as of the logic swing, which determines the Noise Margin. Therefore, this delay model simply relates the speed performance, the power consumption and the Noise Margin of PFSCL gates, and accounts for the dependence on the fan-in and fan-out. Extensive SPICE simulations with a 0.18-m CMOS process confirm the adequate accuracy of the analytical models and the validity of the approximations introduced to simplify the analysis, and a practical design example of an equality comparator is also presented. In order to derive clear guidelines to manage the delay-power-Noise Margin tradeoff, PFSCL gates are analyzed in typical design cases (i.e., design for high speed, low power and power efficiency). For the sake of completeness, the effect of each design parameter on the silicon area occupied by a PFSCL gate is also qualitatively analyzed. The resulting criteria are thus useful to design PFSCL gates without resorting to time-consuming design iterations with a trial and error approach based on simulations.
Mohammad Sharifkhani - One of the best experts on this subject based on the ideXlab platform.
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statistical analysis of read static Noise Margin for near sub threshold sram cell
IEEE Transactions on Circuits and Systems, 2014Co-Authors: Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow HajsadeghiAbstract:A fast statistical method for the analysis of the Read SNM of a 6 T SRAM cell in near/subthreshold region is proposed. The method is based on the nonlinear behavior of the cell. DIBL and body effects are thoroughly considered in the derivation of an accurate closed form solution for the Read Static Noise Margin (SNM) of the near/subthreshold SRAM cell. This method uses the state space equation to derive the Read SNM of the cell as a function of threshold voltage of cell transistors. This function shows the dependency of the Read SNM on sizing, VDD, temperature, and threshold voltage variations. It provides a fast reliability analysis for a cell array of a given size and a supply voltage. It also calculates the accurate value of failure probability of the cell. The analytical results are verified using Monte-Carlo simulations in 45 nm Predictive Technology Models.
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An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 $\mu$ m CMOS
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Mohammad Sharifkhani, Manoj SachdevAbstract:Based on the dynamic criteria for data stability, we introduce segmented virtual grounding architecture with extended read, write Noise Margin to realize a low leakage current, energy efficient SRAM module. The architecture offers subthreshold operation for the entire module, except for the selected segments. In addition, a new operational mode for the SRAM cell is introduced which allows only the bitlines of the selected columns to be discharged in an operation. The stability of the cells is enhanced in both read and write operation by controlling the cell access time and cell supply voltage, respectively. A 2048 times 20 bit eSRAM unit is implemented in a regular 0.13 mum CMOS technology to confirm the idea. The unit operates at 100 MHz and consumes less than 1 mW in both read and write operations. Thanks to the reverse body bias of the transistors, the leakage current of a 0.4 V cell drops to 27 pA during the non-access time. The measurement results shows a 28% Noise Margin enhancement for this scheme when a subthreshold cell is accessed.
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an energy efficient 40 kb sram module with extended read write Noise Margin in 0 13 mu m cmos
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Mohammad Sharifkhani, Manoj SachdevAbstract:Based on the dynamic criteria for data stability, we introduce segmented virtual grounding architecture with extended read, write Noise Margin to realize a low leakage current, energy efficient SRAM module. The architecture offers subthreshold operation for the entire module, except for the selected segments. In addition, a new operational mode for the SRAM cell is introduced which allows only the bitlines of the selected columns to be discharged in an operation. The stability of the cells is enhanced in both read and write operation by controlling the cell access time and cell supply voltage, respectively. A 2048 times 20 bit eSRAM unit is implemented in a regular 0.13 mum CMOS technology to confirm the idea. The unit operates at 100 MHz and consumes less than 1 mW in both read and write operations. Thanks to the reverse body bias of the transistors, the leakage current of a 0.4 V cell drops to 27 pA during the non-access time. The measurement results shows a 28% Noise Margin enhancement for this scheme when a subthreshold cell is accessed.
Massimo Alioto - One of the best experts on this subject based on the ideXlab platform.
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power delay area Noise Margin tradeoffs in positive feedback mos current mode logic
IEEE Transactions on Circuits and Systems I-regular Papers, 2007Co-Authors: Massimo Alioto, L Pancioni, S Rocchi, Valerio VignoliAbstract:In this paper, positive feedback source-coupled logic (PFSCL) gates are analyzed from a design point of view. The design space is explored through analytical relationships which relate the gate delay, power consumption and Noise Margin, which are modeled through a simplified circuit analysis. To be more specific, a simple and accurate model of the Noise Margin is used to derive a systematic design strategy to size the transistors' aspect ratios ensuring an assigned Noise Margin for a given bias current. From the knowledge of the transistor sizes, the gate delay is then expressed as a function of the bias current and the supply voltage, both of which define the static power consumption of PFSCL gates, as well as of the logic swing, which determines the Noise Margin. Therefore, this delay model simply relates the speed performance, the power consumption and the Noise Margin of PFSCL gates, and accounts for the dependence on the fan-in and fan-out. Extensive SPICE simulations with a 0.18-m CMOS process confirm the adequate accuracy of the analytical models and the validity of the approximations introduced to simplify the analysis, and a practical design example of an equality comparator is also presented. In order to derive clear guidelines to manage the delay-power-Noise Margin tradeoff, PFSCL gates are analyzed in typical design cases (i.e., design for high speed, low power and power efficiency). For the sake of completeness, the effect of each design parameter on the silicon area occupied by a PFSCL gate is also qualitatively analyzed. The resulting criteria are thus useful to design PFSCL gates without resorting to time-consuming design iterations with a trial and error approach based on simulations.
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Power–Delay–Area–Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic
IEEE Transactions on Circuits and Systems I-regular Papers, 2007Co-Authors: Massimo Alioto, L Pancioni, S Rocchi, Valerio VignoliAbstract:In this paper, positive feedback source-coupled logic (PFSCL) gates are analyzed from a design point of view. The design space is explored through analytical relationships which relate the gate delay, power consumption and Noise Margin, which are modeled through a simplified circuit analysis. To be more specific, a simple and accurate model of the Noise Margin is used to derive a systematic design strategy to size the transistors' aspect ratios ensuring an assigned Noise Margin for a given bias current. From the knowledge of the transistor sizes, the gate delay is then expressed as a function of the bias current and the supply voltage, both of which define the static power consumption of PFSCL gates, as well as of the logic swing, which determines the Noise Margin. Therefore, this delay model simply relates the speed performance, the power consumption and the Noise Margin of PFSCL gates, and accounts for the dependence on the fan-in and fan-out. Extensive SPICE simulations with a 0.18-m CMOS process confirm the adequate accuracy of the analytical models and the validity of the approximations introduced to simplify the analysis, and a practical design example of an equality comparator is also presented. In order to derive clear guidelines to manage the delay-power-Noise Margin tradeoff, PFSCL gates are analyzed in typical design cases (i.e., design for high speed, low power and power efficiency). For the sake of completeness, the effect of each design parameter on the silicon area occupied by a PFSCL gate is also qualitatively analyzed. The resulting criteria are thus useful to design PFSCL gates without resorting to time-consuming design iterations with a trial and error approach based on simulations.
Pinaki Mazumder - One of the best experts on this subject based on the ideXlab platform.
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dynamic Noise Margin definitions and model
International Conference on VLSI Design, 2004Co-Authors: Li Ding, Pinaki MazumderAbstract:Dynamic Noise analysis is greatly needed in place of traditional static Noise analysis due to the ever increasingly stringent design requirement for VLSI chips based on very deep submicron process technology. In this paper, we propose complete and self-consistent dynamic Noise Margin definitions to reduce the pessimism of conventional static Noise Margin based Noise analysis. A simple and accurate dynamic Noise Margin model is then developed based on a new figure of merit, which is the ratio between the input Noise duration and the sum of gate load capacitance and gate intrinsic capacitance. An efficient dynamic Noise Margin based Noise analysis method is presented.
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VLSI Design - Dynamic Noise Margin: definitions and model
17th International Conference on VLSI Design. Proceedings., 2004Co-Authors: Li Ding, Pinaki MazumderAbstract:Dynamic Noise analysis is greatly needed in place of traditional static Noise analysis due to the ever increasingly stringent design requirement for VLSI chips based on very deep submicron process technology. In this paper, we propose complete and self-consistent dynamic Noise Margin definitions to reduce the pessimism of conventional static Noise Margin based Noise analysis. A simple and accurate dynamic Noise Margin model is then developed based on a new figure of merit, which is the ratio between the input Noise duration and the sum of gate load capacitance and gate intrinsic capacitance. An efficient dynamic Noise Margin based Noise analysis method is presented.
