The Experts below are selected from a list of 1038 Experts worldwide ranked by ideXlab platform
Antonio Sergio Cavalcanti De Menezes - One of the best experts on this subject based on the ideXlab platform.
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Conversão analogico-digital ultra-rapida em corrente em tecnologia bipolar - nova proposta
[s.n.], 2018Co-Authors: Antonio Sergio Cavalcanti De MenezesAbstract:Orientador: Oseas Valente de Avilez FilhoTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia EletricaResumo: Neste trabalho apresentamos uma nova técnica de conversão analógico-digital ultra-rápida de corrente que denominamos semi-flash. Um conversor A/D de 6 bits em tecnologia bipolar todo Npn foi projetado e simulado numericamente pelo programa SPICE 2. Para isso, empregou-se os parâmetros de processo da SID-Microeletrônica ¿ Contagem - Minas Gerais, uma tecnologia de 300 MHz. Também consideramos a tecnologia de 5 GHz e 10 GHz da Plessey Research, Inglaterra ... Observação: O resumo, na íntegra, poderá ser visualizado no texto completo da tese digitalAbstract: In this work we present a new ultra-fast analog-digital conversion technique of current that we named semi-flash. A 6-bit A/D converter, all in bipolar Npn Transistor , was designed and simulated using the computer program SPICE 2. For simulaltion, we consider the process parameters of- the SID-Microelectrônica ¿ Contagam - Minas Gerais, a 300 MHz teachnology. The 5 GHz and 10 GHz technology of the Plessey Research, England, was considered too ... Note: The complete abstract is available with the full electronic digital thesis or dissertationsDoutoradoMestre em Engenharia Elétric
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Conversão analogico-digital ultra-rapida em corrente em tecnologia bipolar - nova proposta
2017Co-Authors: Antonio Sergio Cavalcanti De MenezesAbstract:Resumo: Neste trabalho apresentamos uma nova técnica de conversão analógico-digital ultra-rápida de corrente que denominamos semi-flash. Um conversor A/D de 6 bits em tecnologia bipolar todo Npn foi projetado e simulado numericamente pelo programa SPICE 2. Para isso, empregou-se os parâmetros de processo da SID-Microeletrônica - Contagem - Minas Gerais, uma tecnologia de 300 MHz. Também consideramos a tecnologia de 5 GHz e 10 GHz da Plessey Research, Inglaterra ... Observação: O resumo, na íntegra, poderá ser visualizado no texto completo da tese digitalAbstract: In this work we present a new ultra-fast analog-digital conversion technique of current that we named semi-flash. A 6-bit A/D converter, all in bipolar Npn Transistor , was designed and simulated using the computer program SPICE 2. For simulaltion, we consider the process parameters of- the SID-Microelectrônica - Contagam - Minas Gerais, a 300 MHz teachnology. The 5 GHz and 10 GHz technology of the Plessey Research, England, was considered too ... Note: The complete abstract is available with the full electronic digital thesis or dissertation
C. S. Song - One of the best experts on this subject based on the ideXlab platform.
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Silicon On Insulator) and STI (Shallow Trench
2015Co-Authors: J. H. Kim, S. H. Lee, K. H. Lee, H. J. Park, G. Cha, H. S. Kang, C. S. SongAbstract:In this paper, for the first time, we suggest a novel high voltage, high speed and latch-up free Npn Transistor and PNP Transistor fabricatio
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a high performance complementary bipolar process using pbsoi technique
International Symposium on Power Semiconductor Devices and IC's, 2002Co-Authors: J. H. Kim, K. H. Lee, H. J. Park, G. Cha, H. S. Kang, Sukkyun Lee, C. S. SongAbstract:In this paper, for the first time, we suggest a novel high voltage, high speed and latch-up free Npn Transistor and PNP Transistor fabrication technology using PBSOI (Patterned and Bonded Silicon On Insulator) and STI (Shallow Trench Isolation) technology. Using this technique, we can easily control the breakdown voltage (BVceo) without the problem of P+B/L out-diffusion. In this PBSOI process, after diffusion of well (collector), the Buried Layer is diffused on the well. In addition, unlike the prior technology that devices are fabricated in epitaxial layer, the proposed devices are formed in active wafer itself, therefore we can get defect-free devices promising excellent characteristics. The peak fTs for Npn and PNP Transistor are 10 GHz and 9 GHz, the values of BVceo for the Npn and PNP devices are 15 V and 17 V, respectively. Finally, these values were found to be excellent results as shown in the maximum value of Johnson-limit for the fT-BVceo product.
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newly designed isolated resurf ldmos Transistor for 60 v bcd process provides 20 v vertical Npn Transistor
Device Research Conference, 2002Co-Authors: T H Kwon, H. S. Kang, Y S Jeoung, S K Lee, Yongcheol Choi, Cheoljoong Kim, C. S. SongAbstract:RESURF LDMOS Transistors are utilized in high side driver applications and other applications that mandate electrical isolation between source and substrate by using isolated RESURF technology. However, the BCD process using conventional isolated RESURF LDMOS structures cannot provide high efficiency vertical Npn Transistors due to the dependence of the RESURF LDMOS BV/sub dss/ (source to drain breakdown voltage) upon the epi thickness. In this paper, we propose a new isolated RESURF LDMOS. With the use of n-well near the drain region, we can avoid electric field concentration below the drain region. P-well dose, p-well length and extended drain dose should be optimized to reduce surface field of the proposed isolated RESURF LDMOS regardless of epi thickness.
Seonghwan Cho - One of the best experts on this subject based on the ideXlab platform.
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close in phase noise enhanced voltage controlled oscillator employing parasitic v Npn Transistor in cmos process
IEEE Transactions on Microwave Theory and Techniques, 2006Co-Authors: Ilku Nam, Kwyro Lee, Seonghwan ChoAbstract:This paper presents a voltage-controlled oscillator (VCO) with low close-in phase noise by exploiting a parasitic vertical Npn Transistor (V-Npn) as a tail current source in a 0.18-/spl mu/m CMOS process. V-Npn has an inherently low flicker noise (1/f noise) profile compared to CMOS devices. Simple dc and ac characteristics of V-Npn are measured and extracted for design convenience. The proposed VCO that used a V-Npn current source instead of nMOS is verified using a 0.18-/spl mu/m deep n-well CMOS process. Test results of the designed VCO show good figure-of-merit of -87.4 dBc/Hz, -111 dBc/Hz of phase noise at 10 kHz, and 100-kHz offsets while consuming only 540 /spl mu/W from the 1.8-V supply.
H. S. Kang - One of the best experts on this subject based on the ideXlab platform.
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Silicon On Insulator) and STI (Shallow Trench
2015Co-Authors: J. H. Kim, S. H. Lee, K. H. Lee, H. J. Park, G. Cha, H. S. Kang, C. S. SongAbstract:In this paper, for the first time, we suggest a novel high voltage, high speed and latch-up free Npn Transistor and PNP Transistor fabricatio
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a high performance complementary bipolar process using pbsoi technique
International Symposium on Power Semiconductor Devices and IC's, 2002Co-Authors: J. H. Kim, K. H. Lee, H. J. Park, G. Cha, H. S. Kang, Sukkyun Lee, C. S. SongAbstract:In this paper, for the first time, we suggest a novel high voltage, high speed and latch-up free Npn Transistor and PNP Transistor fabrication technology using PBSOI (Patterned and Bonded Silicon On Insulator) and STI (Shallow Trench Isolation) technology. Using this technique, we can easily control the breakdown voltage (BVceo) without the problem of P+B/L out-diffusion. In this PBSOI process, after diffusion of well (collector), the Buried Layer is diffused on the well. In addition, unlike the prior technology that devices are fabricated in epitaxial layer, the proposed devices are formed in active wafer itself, therefore we can get defect-free devices promising excellent characteristics. The peak fTs for Npn and PNP Transistor are 10 GHz and 9 GHz, the values of BVceo for the Npn and PNP devices are 15 V and 17 V, respectively. Finally, these values were found to be excellent results as shown in the maximum value of Johnson-limit for the fT-BVceo product.
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newly designed isolated resurf ldmos Transistor for 60 v bcd process provides 20 v vertical Npn Transistor
Device Research Conference, 2002Co-Authors: T H Kwon, H. S. Kang, Y S Jeoung, S K Lee, Yongcheol Choi, Cheoljoong Kim, C. S. SongAbstract:RESURF LDMOS Transistors are utilized in high side driver applications and other applications that mandate electrical isolation between source and substrate by using isolated RESURF technology. However, the BCD process using conventional isolated RESURF LDMOS structures cannot provide high efficiency vertical Npn Transistors due to the dependence of the RESURF LDMOS BV/sub dss/ (source to drain breakdown voltage) upon the epi thickness. In this paper, we propose a new isolated RESURF LDMOS. With the use of n-well near the drain region, we can avoid electric field concentration below the drain region. P-well dose, p-well length and extended drain dose should be optimized to reduce surface field of the proposed isolated RESURF LDMOS regardless of epi thickness.
Ilku Nam - One of the best experts on this subject based on the ideXlab platform.
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close in phase noise enhanced voltage controlled oscillator employing parasitic v Npn Transistor in cmos process
IEEE Transactions on Microwave Theory and Techniques, 2006Co-Authors: Ilku Nam, Kwyro Lee, Seonghwan ChoAbstract:This paper presents a voltage-controlled oscillator (VCO) with low close-in phase noise by exploiting a parasitic vertical Npn Transistor (V-Npn) as a tail current source in a 0.18-/spl mu/m CMOS process. V-Npn has an inherently low flicker noise (1/f noise) profile compared to CMOS devices. Simple dc and ac characteristics of V-Npn are measured and extracted for design convenience. The proposed VCO that used a V-Npn current source instead of nMOS is verified using a 0.18-/spl mu/m deep n-well CMOS process. Test results of the designed VCO show good figure-of-merit of -87.4 dBc/Hz, -111 dBc/Hz of phase noise at 10 kHz, and 100-kHz offsets while consuming only 540 /spl mu/W from the 1.8-V supply.
