The Experts below are selected from a list of 7527 Experts worldwide ranked by ideXlab platform
Zhi Ning Chen - One of the best experts on this subject based on the ideXlab platform.
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full modeling Loss reduction and mutual coupling control of spoof surface plasmon based meander slow wave transmission lines
IEEE Transactions on Microwave Theory and Techniques, 2018Co-Authors: Amin Kianinejad, Zhi Ning Chen, Chengwei QiuAbstract:The full models of meander spoof surface plasmon (SSP) cells are presented for the design of slow wave transmission lines (SW-TLs) with the minimum Loss and controllable mutual coupling (MC). In addition to the modeling of dispersion curve and characteristic impedance, the proposed circuit model based on geometrical parameters calculates the Ohmic Loss of the SW-TLs composed of meander SSP cells. Being verified with the full-wave analysis, the model provides a clear understanding of the mechanism of the SSP-based SW-TLs and a new way to design with other circuits at a system level. The model is applied to minimize the Ohmic Loss in the meander SW-TLs up to at least 10 dB per 10 wavelengths lower than that of conventional TLs. The MC of the SW-TLs can be controlled either up to three orders of magnitude lower or one order of magnitude higher than that of the conventional TLs. This paper proposes methods to decrease the Ohmic Loss of single-layered meander SW-TLs and also controls MC between them. The proposed methods open new avenues for complex and compact circuit designs.
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low Loss spoof surface plasmon slow wave transmission lines with compact transition and high isolation
IEEE Transactions on Microwave Theory and Techniques, 2016Co-Authors: Amin Kianinejad, Zhi Ning ChenAbstract:The symmetric spoof surface plasmon (SSP)-based slow-wave transmission line (SW-TL) with compact transition, low Ohmic Loss, and low crosstalk between SW-TLs is proposed and investigated. First, the SSP cells are modeled by equivalent circuit elements. The proposed equivalent circuit model is appealing for the integration of SW-TLs with other microwave circuits. With the symmetricity, the SW-TLs are readily realized by a compact mode converter providing gradual impedance, momentum, and polarization matching from guided waves to spoof microwave plasmons. Then, simulation studies and experiments verify that the proposed SSP SW-TL features as low as half the Ohmic Loss of the traditional counterparts. After that, the low mutual coupling between the proposed SSP SW-TLs is numerically and experimentally substantiated and showed to be up to 10 dB lower than that between conventional microstrip TLs. The proposed low Loss, highly isolated and compact SW-TL along with the reliable circuit model enables the further exploitation of promising spoof plasmon modes in microwave technology.
Amin Kianinejad - One of the best experts on this subject based on the ideXlab platform.
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full modeling Loss reduction and mutual coupling control of spoof surface plasmon based meander slow wave transmission lines
IEEE Transactions on Microwave Theory and Techniques, 2018Co-Authors: Amin Kianinejad, Zhi Ning Chen, Chengwei QiuAbstract:The full models of meander spoof surface plasmon (SSP) cells are presented for the design of slow wave transmission lines (SW-TLs) with the minimum Loss and controllable mutual coupling (MC). In addition to the modeling of dispersion curve and characteristic impedance, the proposed circuit model based on geometrical parameters calculates the Ohmic Loss of the SW-TLs composed of meander SSP cells. Being verified with the full-wave analysis, the model provides a clear understanding of the mechanism of the SSP-based SW-TLs and a new way to design with other circuits at a system level. The model is applied to minimize the Ohmic Loss in the meander SW-TLs up to at least 10 dB per 10 wavelengths lower than that of conventional TLs. The MC of the SW-TLs can be controlled either up to three orders of magnitude lower or one order of magnitude higher than that of the conventional TLs. This paper proposes methods to decrease the Ohmic Loss of single-layered meander SW-TLs and also controls MC between them. The proposed methods open new avenues for complex and compact circuit designs.
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low Loss spoof surface plasmon slow wave transmission lines with compact transition and high isolation
IEEE Transactions on Microwave Theory and Techniques, 2016Co-Authors: Amin Kianinejad, Zhi Ning ChenAbstract:The symmetric spoof surface plasmon (SSP)-based slow-wave transmission line (SW-TL) with compact transition, low Ohmic Loss, and low crosstalk between SW-TLs is proposed and investigated. First, the SSP cells are modeled by equivalent circuit elements. The proposed equivalent circuit model is appealing for the integration of SW-TLs with other microwave circuits. With the symmetricity, the SW-TLs are readily realized by a compact mode converter providing gradual impedance, momentum, and polarization matching from guided waves to spoof microwave plasmons. Then, simulation studies and experiments verify that the proposed SSP SW-TL features as low as half the Ohmic Loss of the traditional counterparts. After that, the low mutual coupling between the proposed SSP SW-TLs is numerically and experimentally substantiated and showed to be up to 10 dB lower than that between conventional microstrip TLs. The proposed low Loss, highly isolated and compact SW-TL along with the reliable circuit model enables the further exploitation of promising spoof plasmon modes in microwave technology.
Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.
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minimizing Ohmic Loss in future processor ir events
International Symposium on Quality Electronic Design, 2006Co-Authors: Mark M Budnik, Kaushik RoyAbstract:IR events are periods in time when processors draw a high level of steady state operating current. During IR events, Ohmic Losses occur in the power delivery path. To minimize these Ohmic Losses, conventional systems use parallelism to reduce the resistance of the power delivery path. As operating currents continue to increase, however, additional remedies may be required to maintain acceptable Ohmic Losses. We show how a processor with integrated step down converters can be used to reduce the Ohmic Loss in its power delivery path. In a 130nm technology node, our integrated solution can reduce the delivery path Ohmic Loss by 32.8%.
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minimizing Ohmic Loss and supply voltage variation using a novel distributed power supply network
Design Automation and Test in Europe, 2006Co-Authors: Mark M Budnik, Kaushik RoyAbstract:IR and di/dt events may cause Ohmic Losses and large supply voltage variations due to system parasitics. Today, parallelism in the power delivery path is used to reduce Ohmic Loss while decoupling capacitance is used to minimize the supply voltage variation. Future integrated circuits, however, will exhibit large enough currents and current transients to mandate additional safeguards. A novel, distributed power delivery and decoupling network is introduced reducing the supply voltage variation magnitude by 67% and the future Ohmic Loss by 15.9W (compared to today’s power delivery and decoupling networks) using conventional processing and packaging techniques in a 130nm technology node.
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DATE - Minimizing Ohmic Loss and Supply Voltage Variation Using a Novel Distributed Power Supply Network
Proceedings of the Design Automation & Test in Europe Conference, 2006Co-Authors: Mark M Budnik, Kaushik RoyAbstract:IR and di/dt events may cause Ohmic Losses and large supply voltage variations due to system parasitics. Today, parallelism in the power delivery path is used to reduce Ohmic Loss while decoupling capacitance is used to minimize the supply voltage variation. Future integrated circuits, however, will exhibit large enough currents and current transients to mandate additional safeguards. A novel, distributed power delivery and decoupling network is introduced reducing the supply voltage variation magnitude by 67% and the future Ohmic Loss by 15.9W (compared to today’s power delivery and decoupling networks) using conventional processing and packaging techniques in a 130nm technology node.
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A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006Co-Authors: Mark M Budnik, Kaushik RoyAbstract:di/dt and IR events may cause large supply voltage variations and Ohmic Losses due to system parasitics. Today, decoupling capacitance is used to minimize the supply voltage variation, and parallelism in the power delivery path is used to reduce Ohmic Loss. Future integrated circuits, however, will exhibit large enough currents and current transients to mandate additional safeguards. A novel, distributed power delivery and decoupling network is introduced that reduces the supply voltage variation magnitude by more than 66% or the future Ohmic Loss by more than 27% (compared to today's power delivery and decoupling networks) using conventional processing and packaging techniques
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ISQED - Minimizing Ohmic Loss in Future Processor IR Events
7th International Symposium on Quality Electronic Design (ISQED'06), 1Co-Authors: Mark M Budnik, Kaushik RoyAbstract:IR events are periods in time when processors draw a high level of steady state operating current. During IR events, Ohmic Losses occur in the power delivery path. To minimize these Ohmic Losses, conventional systems use parallelism to reduce the resistance of the power delivery path. As operating currents continue to increase, however, additional remedies may be required to maintain acceptable Ohmic Losses. We show how a processor with integrated step down converters can be used to reduce the Ohmic Loss in its power delivery path. In a 130nm technology node, our integrated solution can reduce the delivery path Ohmic Loss by 32.8%.
Chengwei Qiu - One of the best experts on this subject based on the ideXlab platform.
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full modeling Loss reduction and mutual coupling control of spoof surface plasmon based meander slow wave transmission lines
IEEE Transactions on Microwave Theory and Techniques, 2018Co-Authors: Amin Kianinejad, Zhi Ning Chen, Chengwei QiuAbstract:The full models of meander spoof surface plasmon (SSP) cells are presented for the design of slow wave transmission lines (SW-TLs) with the minimum Loss and controllable mutual coupling (MC). In addition to the modeling of dispersion curve and characteristic impedance, the proposed circuit model based on geometrical parameters calculates the Ohmic Loss of the SW-TLs composed of meander SSP cells. Being verified with the full-wave analysis, the model provides a clear understanding of the mechanism of the SSP-based SW-TLs and a new way to design with other circuits at a system level. The model is applied to minimize the Ohmic Loss in the meander SW-TLs up to at least 10 dB per 10 wavelengths lower than that of conventional TLs. The MC of the SW-TLs can be controlled either up to three orders of magnitude lower or one order of magnitude higher than that of the conventional TLs. This paper proposes methods to decrease the Ohmic Loss of single-layered meander SW-TLs and also controls MC between them. The proposed methods open new avenues for complex and compact circuit designs.
Mark M Budnik - One of the best experts on this subject based on the ideXlab platform.
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minimizing Ohmic Loss in future processor ir events
International Symposium on Quality Electronic Design, 2006Co-Authors: Mark M Budnik, Kaushik RoyAbstract:IR events are periods in time when processors draw a high level of steady state operating current. During IR events, Ohmic Losses occur in the power delivery path. To minimize these Ohmic Losses, conventional systems use parallelism to reduce the resistance of the power delivery path. As operating currents continue to increase, however, additional remedies may be required to maintain acceptable Ohmic Losses. We show how a processor with integrated step down converters can be used to reduce the Ohmic Loss in its power delivery path. In a 130nm technology node, our integrated solution can reduce the delivery path Ohmic Loss by 32.8%.
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minimizing Ohmic Loss and supply voltage variation using a novel distributed power supply network
Design Automation and Test in Europe, 2006Co-Authors: Mark M Budnik, Kaushik RoyAbstract:IR and di/dt events may cause Ohmic Losses and large supply voltage variations due to system parasitics. Today, parallelism in the power delivery path is used to reduce Ohmic Loss while decoupling capacitance is used to minimize the supply voltage variation. Future integrated circuits, however, will exhibit large enough currents and current transients to mandate additional safeguards. A novel, distributed power delivery and decoupling network is introduced reducing the supply voltage variation magnitude by 67% and the future Ohmic Loss by 15.9W (compared to today’s power delivery and decoupling networks) using conventional processing and packaging techniques in a 130nm technology node.
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DATE - Minimizing Ohmic Loss and Supply Voltage Variation Using a Novel Distributed Power Supply Network
Proceedings of the Design Automation & Test in Europe Conference, 2006Co-Authors: Mark M Budnik, Kaushik RoyAbstract:IR and di/dt events may cause Ohmic Losses and large supply voltage variations due to system parasitics. Today, parallelism in the power delivery path is used to reduce Ohmic Loss while decoupling capacitance is used to minimize the supply voltage variation. Future integrated circuits, however, will exhibit large enough currents and current transients to mandate additional safeguards. A novel, distributed power delivery and decoupling network is introduced reducing the supply voltage variation magnitude by 67% and the future Ohmic Loss by 15.9W (compared to today’s power delivery and decoupling networks) using conventional processing and packaging techniques in a 130nm technology node.
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A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006Co-Authors: Mark M Budnik, Kaushik RoyAbstract:di/dt and IR events may cause large supply voltage variations and Ohmic Losses due to system parasitics. Today, decoupling capacitance is used to minimize the supply voltage variation, and parallelism in the power delivery path is used to reduce Ohmic Loss. Future integrated circuits, however, will exhibit large enough currents and current transients to mandate additional safeguards. A novel, distributed power delivery and decoupling network is introduced that reduces the supply voltage variation magnitude by more than 66% or the future Ohmic Loss by more than 27% (compared to today's power delivery and decoupling networks) using conventional processing and packaging techniques
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ISQED - Minimizing Ohmic Loss in Future Processor IR Events
7th International Symposium on Quality Electronic Design (ISQED'06), 1Co-Authors: Mark M Budnik, Kaushik RoyAbstract:IR events are periods in time when processors draw a high level of steady state operating current. During IR events, Ohmic Losses occur in the power delivery path. To minimize these Ohmic Losses, conventional systems use parallelism to reduce the resistance of the power delivery path. As operating currents continue to increase, however, additional remedies may be required to maintain acceptable Ohmic Losses. We show how a processor with integrated step down converters can be used to reduce the Ohmic Loss in its power delivery path. In a 130nm technology node, our integrated solution can reduce the delivery path Ohmic Loss by 32.8%.
