The Experts below are selected from a list of 84000 Experts worldwide ranked by ideXlab platform
Johann W. Kolar - One of the best experts on this subject based on the ideXlab platform.
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comparison of 3 phase wide Output voltage range pwm rectifiers
IEEE Transactions on Industrial Electronics, 2007Co-Authors: T Nussbaumer, Johann W. KolarAbstract:A three-phase buck boost pulsewidth modulation (PWM) rectifier with a three-switch buck-type rectifier input Stage and an integrated dc/dc boost converter Output Stage, and a three-phase boost buck PWM rectifier system formed by series connection of a boost-type rectifier input Stage (Vienna Rectifier) and a dc/dc buck converter Output Stage are presented and comparatively evaluated. Both systems are characterized by sinusoidal input current and wide Output voltage control range. The comparison is for 6 kW rated Output power at 400 Vrms line-to-line input and variable Output voltage 200 V 600 V and identifies the buck boost approach as significantly superior regarding the overall efficiency, the volume and weight of the passive power components, and the overall system complexity.
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novel hybrid 12 pulse line interphase transformer boost type rectifier with controlled Output voltage and sinusoidal utility currents
Ieej Transactions on Industry Applications, 2007Co-Authors: Kazuaki Mino, Y Nishida, Johann W. KolarAbstract:∗∗ Member ∗ A novel injection scheme to improve the input current harmonics of a hybrid 12-pulse line-interphase-transformer rectifier with controlled Output voltage by a two-switch boost-type Output Stage is presented in this paper. A theoretical derivation of the modulation for achieving purely sinusoidal input currents is introduced. Finally, the proposed scheme is analyzed and verified by numerical simulations and experimental results.
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a novel control concept for reliable operation of a three phase three switch buck type unity power factor rectifier with integrated boost Output Stage under heavily unbalanced mains condition
Power Electronics Specialists Conference, 2005Co-Authors: M Baumann, Johann W. KolarAbstract:In this paper the reliable operation of a three-phase three-switch buck-type pulsewidth-modulation unity-power-factor rectifier with integrated boost Output Stage under heavily unbalanced mains, i.e., mains voltage unbalance, loss of one phase, short circuit of two phases, or earth fault of one phase is investigated theoretically and experimentally. A brief description of the principle of operation and the most advantageous modulation method are given. The analytical calculation of the relative on-times of the active switching states and of the dc-link current reference value is treated in detail for active and deactivated boost Output Stage. Based on the theoretical considerations a control scheme which allows for controlling the system for any mains condition without changeover of the control structure is described. Furthermore, digital simulations as well as experimental results are shown which confirm the proposed control concept for different mains failure conditions and for the transition from balanced mains to a failure condition and vice versa. The experimental results are derived from a 5-kW prototype (input voltage range (280...480) V/sub rms/ line-to-line, Output voltage 400 V/sub DC/) of the rectifier system, where the control is realized by a 32-bit digital signal processor.
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a novel control concept for reliable operation of a three phase three switch buck type unity power factor rectifier with integrated boost Output Stage under heavily unbalanced mains condition
IEEE Annual Conference on Power Electronics Specialist, 2003Co-Authors: M Baumann, Johann W. KolarAbstract:In this paper the reliable operation of a three-phase three-switch buck-type PWM unity power factor rectifier with integrated boost Output Stage under heavily unbalanced mains, i.e. mains voltage unbalance, loss of one phase, short circuit of two phases or earth fault of one phase is investigated theoretically and experimentally. The analytical calculation of the relative on-times of the active switching states and of the DC link current reference value is treated in detail for active and deactivated boost Output Stage. Based on the theoretical considerations a control scheme which allows to control the system for any mains condition without change-over of the control structure is described. Furthermore, digital simulations as well as experimental results are shown which confirm the proposed control concept for different mains failure conditions and for the transition from balanced mains to a failure condition and vice versa. The experimental results are derived from a 5 kW prototype, input voltage range 208-480 V/sub rms/ line-to-line, Output voltage 400 V/sub DC/ of the rectifier system, where the control is realized by a 32-bit digital signal processor.
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minimization of the dc current ripple of a three phase buck boost pwm unity power factor rectifier
Power Conversion Conference, 2002Co-Authors: M Baumann, Johann W. KolarAbstract:The modulation of a novel three-phase three-switch buck-type unity power factor rectifier with integrated DC/DC boost converter Output Stage is optimized concerning the ripple amplitude of the buck-boost inductor current. This is achieved by coordination of the switching operation of the buck input Stage and of the boost Output Stage. A comparative evaluation of different modulation schemes does identify a modulation scheme which simultaneously does provide minimum DC current ripple and minimum input filter capacitor voltage ripple at minimum switching losses and/or maximum pulse frequency. All theoretical considerations are for operation in a wide input voltage range and are verified by simulations and by measurements on a DSP-controlled 5 k W prototype of the system.
S Pennisi - One of the best experts on this subject based on the ideXlab platform.
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low power high speed rail to rail lcd Output buffer with dual path push pull operation and quiescent current control
Analog Integrated Circuits and Signal Processing, 2010Co-Authors: D Marano, G Palumbo, S PennisiAbstract:The present paper addresses a new compact low-power high-speed Output buffer amplifier topology for large-size liquid crystal display applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by simultaneously exploiting the push---pull Output sections of two basic complementary-type input amplifiers to realize a dual-path push---pull operation of the Output Stage. An auxiliary biasing network integrated in the input differential Stage allows the quiescent bias conditions of the class-AB Output Stage to be inherently controlled without additional current dissipation. Post-layout simulation results confirm that the proposed amplifier can drive a 1-nF column line load within a 0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current. Monte Carlo simulations are finally carried out, showing a good degree of robustness of the proposed Output buffer against process and mismatch variations.
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a new compact low power high speed rail to rail class b buffer for lcd applications
IEEE\ OSA Journal of Display Technology, 2010Co-Authors: D Marano, G Palumbo, S PennisiAbstract:This paper addresses a very compact low-power class-B buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance, draws a small quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by exploiting two current comparators embodied in the input Stage, which sense the input signal transients to turn on the Output Stage transistors. A rail-to-rail stacked mirror differential amplifier is used to amplify the input signal difference and supply the bias voltages for the Output Stage. Post-layout simulations show that the proposed buffer can drive a 1-nF column line load within 1.8-?s settling time under a full voltage swing, while drawing only 3.5-?A static current from a 3-V power supply. Monte Carlo results finally confirm an excellent degree of robustness of the proposed topology.
Joseph S Chang - One of the best experts on this subject based on the ideXlab platform.
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an investigation into the parameters affecting total harmonic distortion in low voltage low power class d amplifiers
IEEE Transactions on Circuits and Systems I-regular Papers, 2003Co-Authors: Meng Tong Tan, Hockchuan Chua, Joseph S Chang, Bahhwee GweeAbstract:We investigate the influence of two important practical design parameters on total harmonic distortion (THD) for the design of low-voltage (0.9-1.4 V) low-power analog Class-D amplifiers: the linearity of the carrier waveform and the impedance of the Output Stage. We show that the carrier nonlinearity results in THD and propose a novel mathematical analysis method to model the nonlinearity. We recommend a range of the parameter that describes the carrier nonlinearity and that results in a good compromise to the dynamic range of the pulsewidth modulator of the Class-D amplifier. We show that the impedance of the Output Stage has little effect on THD. We verify our analyses by means of MATLAB and HSPICE computer simulations, and on the basis of practical measurements.
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analysis and design of power efficient class d amplifier Output Stages
IEEE Transactions on Circuits and Systems I-regular Papers, 2000Co-Authors: Joseph S Chang, Meng Tong Tan, Zhihong Cheng, Y C TongAbstract:A Class D amplifier comprises a pulse width modulator and an Output Stage. In this paper we analyze the power dissipation mechanisms and derive the overall power efficiency of the Output Stage realized using the finger and waffle layouts. We compare the relative merits of these layouts; we propose two design methodologies to determine the aspect ratios of the transistors in the Output Stage for optimum power efficiency (optimum for a given fabrication process, supply voltage and load resistance): (1) optimization to a single modulation index point and (2) optimization to a range of modulation indexes. For the design of an Output Stage with optimum power efficiency (and small IC area), we recommend optimization to a range of modulation indexes and a layout realized by the waffle structure. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype ICs.
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an investigation on the parameters affecting total harmonic distortion in class d amplifiers
International Symposium on Circuits and Systems, 2000Co-Authors: Meng Tong Tan, Hockchuan Chua, Bahhwee Gwee, Joseph S ChangAbstract:In this paper, we investigate two important and practical design parameters for the design of low-voltage low-power class D amplifiers that may affect the Total Harmonic Distortion (THD): the linearity of the carrier waveform and the impedance of the Output Stage. By means of a novel mathematical analysis method to model the carrier non-linearity, we show that this non-linearity should be mitigated to achieve low THD. Our mathematical analysis also provides an insight to the degree of non-linearity acceptable for a practical design. We show that the impedance of the Output Stage has little effect on THD. We verify our analysis by means of MATLAB and SPICE simulations.
Meng Tong Tan - One of the best experts on this subject based on the ideXlab platform.
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an investigation into the parameters affecting total harmonic distortion in low voltage low power class d amplifiers
IEEE Transactions on Circuits and Systems I-regular Papers, 2003Co-Authors: Meng Tong Tan, Hockchuan Chua, Joseph S Chang, Bahhwee GweeAbstract:We investigate the influence of two important practical design parameters on total harmonic distortion (THD) for the design of low-voltage (0.9-1.4 V) low-power analog Class-D amplifiers: the linearity of the carrier waveform and the impedance of the Output Stage. We show that the carrier nonlinearity results in THD and propose a novel mathematical analysis method to model the nonlinearity. We recommend a range of the parameter that describes the carrier nonlinearity and that results in a good compromise to the dynamic range of the pulsewidth modulator of the Class-D amplifier. We show that the impedance of the Output Stage has little effect on THD. We verify our analyses by means of MATLAB and HSPICE computer simulations, and on the basis of practical measurements.
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analysis and design of power efficient class d amplifier Output Stages
IEEE Transactions on Circuits and Systems I-regular Papers, 2000Co-Authors: Joseph S Chang, Meng Tong Tan, Zhihong Cheng, Y C TongAbstract:A Class D amplifier comprises a pulse width modulator and an Output Stage. In this paper we analyze the power dissipation mechanisms and derive the overall power efficiency of the Output Stage realized using the finger and waffle layouts. We compare the relative merits of these layouts; we propose two design methodologies to determine the aspect ratios of the transistors in the Output Stage for optimum power efficiency (optimum for a given fabrication process, supply voltage and load resistance): (1) optimization to a single modulation index point and (2) optimization to a range of modulation indexes. For the design of an Output Stage with optimum power efficiency (and small IC area), we recommend optimization to a range of modulation indexes and a layout realized by the waffle structure. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype ICs.
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an investigation on the parameters affecting total harmonic distortion in class d amplifiers
International Symposium on Circuits and Systems, 2000Co-Authors: Meng Tong Tan, Hockchuan Chua, Bahhwee Gwee, Joseph S ChangAbstract:In this paper, we investigate two important and practical design parameters for the design of low-voltage low-power class D amplifiers that may affect the Total Harmonic Distortion (THD): the linearity of the carrier waveform and the impedance of the Output Stage. By means of a novel mathematical analysis method to model the carrier non-linearity, we show that this non-linearity should be mitigated to achieve low THD. Our mathematical analysis also provides an insight to the degree of non-linearity acceptable for a practical design. We show that the impedance of the Output Stage has little effect on THD. We verify our analysis by means of MATLAB and SPICE simulations.
D Marano - One of the best experts on this subject based on the ideXlab platform.
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low power high speed rail to rail lcd Output buffer with dual path push pull operation and quiescent current control
Analog Integrated Circuits and Signal Processing, 2010Co-Authors: D Marano, G Palumbo, S PennisiAbstract:The present paper addresses a new compact low-power high-speed Output buffer amplifier topology for large-size liquid crystal display applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by simultaneously exploiting the push---pull Output sections of two basic complementary-type input amplifiers to realize a dual-path push---pull operation of the Output Stage. An auxiliary biasing network integrated in the input differential Stage allows the quiescent bias conditions of the class-AB Output Stage to be inherently controlled without additional current dissipation. Post-layout simulation results confirm that the proposed amplifier can drive a 1-nF column line load within a 0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current. Monte Carlo simulations are finally carried out, showing a good degree of robustness of the proposed Output buffer against process and mismatch variations.
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a new compact low power high speed rail to rail class b buffer for lcd applications
IEEE\ OSA Journal of Display Technology, 2010Co-Authors: D Marano, G Palumbo, S PennisiAbstract:This paper addresses a very compact low-power class-B buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance, draws a small quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by exploiting two current comparators embodied in the input Stage, which sense the input signal transients to turn on the Output Stage transistors. A rail-to-rail stacked mirror differential amplifier is used to amplify the input signal difference and supply the bias voltages for the Output Stage. Post-layout simulations show that the proposed buffer can drive a 1-nF column line load within 1.8-?s settling time under a full voltage swing, while drawing only 3.5-?A static current from a 3-V power supply. Monte Carlo results finally confirm an excellent degree of robustness of the proposed topology.
