The Experts below are selected from a list of 49131 Experts worldwide ranked by ideXlab platform
Le Luo - One of the best experts on this subject based on the ideXlab platform.
-
A new designed trench structure to reduce the wafer warpage in wafer level Packaging Process
2014 15th International Conference on Electronic Packaging Technology, 2014Co-Authors: Chunsheng Zhu, Heng Lee, Le LuoAbstract:Wafer warpage in wafer level Packaging Process poses threats to wafer handling, Process qualities, and can also lead to unacceptable reliability problems. With larger diameter wafer adopted, this issue becomes more serious. In the paper, a new designed trench structure was introduced in WLP Process to reduce the final wafer warpage. Both experiment and simulation methods are used to investigated the effect of the trenches on the wafer warpage. The result indicates that, by forming deep trenches, the stress of individual dies is decoupled and the total the wafer warpage will be decreased. The effect of the geometry of these trenches on the mechanical behavior of the wafer was further studied by simulation.
-
experimental identification of warpage origination during the wafer level Packaging Process
Electronic Components and Technology Conference, 2014Co-Authors: Chunsheng Zhu, Heng Lee, Wenguo Ning, Le LuoAbstract:Redistribution layer (RDL) composing of polyimide (PI) dielectric layer and electro-chemical deposited (ECD) Cu trace is a critical part for wafer level Packaging (WLP). One concern of this multi-layered film structure is the wafer warpage induced during the Process, which poses threats to automatic handling, 3-D integration and device reliability. In this paper, the warpage origination during the WLP Process was identified and analyzed by experiments and simulations. The wafer warpage evolution during the WLP Process was measured by a Multi-beam Optical Sensor system. We found that the cure shrinkage of PI has little effect on the warpage, however, it is mainly caused by the coefficient of thermal expansion (CTE) mismatch between the deposited materials. The ECD Cu trace in RDL accounted for a substantial proportion to the total wafer warpage and lead to a hysteresis response during the thermal Processes indicating plastic deformation has taken place. For in-depth understanding, the plastic behavior of ECD Cu film was investigated and the kinematic hardening plastic model was established. Finally, the stresses distribution in RDL structure was simulated by numerical method and the influence of ECD Cu trace pattern on the wafer warpage was evaluated.
-
Vacuum Packaging Process Simulation for MEMS Devices
2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, 2005Co-Authors: Yingjun Cheng, Dapeng Zhu, Le LuoAbstract:By applying vacuum physics to typical solder reflow vacuum Packaging Process of MEMS devices, the mathematical and physical model of the vacuum degree change of the cavity to be sealed in related with the gas absorption, desorption, penetration, flowage through little pipe and vapour pressure of materials was established and its arithmetic was ascertained with numerical simulation method. A software module with friendly interface was developed by Visual C++ programming, which comprises results view and parameters input interfaces such as gas parameters input, Packaging structure input, reflow time and heating profile input and gas discharging performance input. The veracity of the simulation results was validated by a simulated vacuum Packaging experiment, and the effects of the size of capillary pipe and heating profile of solder reflow Process on vacuum degree were analyzed based on the simulation results. The parametrical modeling, simulation and optimization design of vacuum Packaging Process of MEMS devices was realized
G Q Lo - One of the best experts on this subject based on the ideXlab platform.
-
silicon photonics Packaging with lateral fiber coupling to apodized grating coupler embedded circuit
Optics Express, 2014Co-Authors: Chao Li, Koh Sing Chee, Huijuan Zhang, Mingbin Yu, G Q LoAbstract:We report a novel lateral Packaging approach using laser welding technique with angle polished fiber coupling to grating coupler embedded silicon photonic circuit. Measurements show the relax alignment tolerance for fiber Packaging Process. The Packaging excess loss of 1.2 dB is achieved. The use of angle polished fiber for lateral fiber coupling enables an alternative way for cost-effective deployment of silicon photonics Packaging in telecommunication systems.
Baoshun Zhang - One of the best experts on this subject based on the ideXlab platform.
-
wafer level light emitting diode wl led chip simplified package for very high power solid state lighting ssl source
IEEE Electron Device Letters, 2016Co-Authors: Yibin Zhang, Jianwei Xu, Mingdi Ding, Desheng Zhao, Hongjuan Huang, Guojun Lu, Zhenlin Miao, Yundong Qi, Baoshun ZhangAbstract:A simplified Packaging Process was successfully developed for a wafer-level light emitting diode (WL-LED) chip aiming at very-high power solid-state lighting (SSL) applications. Compared with the traditional chip-on-board (COB) technology, WL-LED chip not only greatly simplifies the Packaging Process but also enables the lighting source more compact. The fabricated blue WL-LED SSL source with a record-high light output power of 305 W exhibits $\sim 30$ % wall plug efficiency at an input electrical power of 1026 W.
Dean M. Aslam - One of the best experts on this subject based on the ideXlab platform.
-
NEMS - Thin film Packaging Process for MEMS device using polycrystalline diamond
2010 IEEE 5th International Conference on Nano Micro Engineered and Molecular Systems, 2010Co-Authors: Zongliang Cao, Dean M. AslamAbstract:This work reports two designs of a poly-C thin film Packaging Process, each including an encapsulated poly-C device. The 1st design uses boron-doped poly-C as electrical feedthroughs which can be embedded into the undoped, electrically insulating poly-C package. Access ports were opened along the package edge to release the thin film package and the device. Then, additional poly-C growth was used to seal the access ports. The 2nd design is based on the concept of using porous diamond to release the structures from the top of the package, thereby significantly reducing the release and sealing time of the package, without significantly affecting the device. A preliminary test regarding the package's fluidic hermeticity was performed to demonstrate that the poly-C thin film package has good fluidic hermeticity in an acidic environment. This is the first time that porous diamond created by RIE has been used in all-diamond thin film Packaging including poly-C electrical feedthroughs, and a poly-C encapsulated device has been reported.
-
The application of polycrystalline diamond in a thin film Packaging Process for MEMS resonators
Diamond and Related Materials, 2006Co-Authors: Xiangwei Zhu, Dean M. Aslam, John P. SullivanAbstract:Abstract This paper reports the design, fabrication and testing of a polycrystalline diamond (poly-C) thin film Packaging Process for a MEMS cantilever type resonator using a 4-mask fabrication Process, which integrates chemical vapor deposition (CVD) diamond thin film technology with an encapsulation Packaging Process. After poly-C cantilever beam resonators were fabricated using the first two masks, a sacrificial PECVD SiO 2 layer with a thickness in the range of 4–5 μm was deposited at 350 °C and patterned to create the package anchor. Then, a 4-μm-thick poly-C film was grown and patterned to create the thin film Packaging structure containing fluidic access ports for the removal of the sacrificial layer. The fluidic access ports were finally sealed with an additional poly-C growth. To evaluate the efficacy of the poly-C encapsulation Process, poly-C cantilever beam resonators were tested using a piezoelectric actuation and laser detection method before and after the poly-C Packaging Process. Resonance frequencies measured before and after are in the range of 240–320 kHz, which is consistent with predicted calculations. A modified fabrication Process was designed to test the fluidic hermiticity of the thin film package.
Wen-bin Young - One of the best experts on this subject based on the ideXlab platform.
-
Modeling and numerical study of thermal-compression bonding in the Packaging Process using NCA
Applied Mathematical Modelling, 2014Co-Authors: Ching Ho Chang, Wen-bin YoungAbstract:Abstract Packaging technology used in liquid crystal displays (LCDs) faces the critical issues such as high density interconnects, thinner Packaging size, and environmental safety. In order to reduce the Packaging size, driver integrated circuit (IC) chips are directly attached to LCD panels using flip chip technology with adhesives, which is called chip on glass (COG) Packaging Processes. To investigate the effects of the bonding force and bonding temperature on the flip chip thermal-compression Packaging, this study established a compression model to analyze the flip chip Packaging Processes with non-conductive adhesives (NCAs). The plastic deformation of bumps and the NCA flow dynamics between chip and substrate were taken into account in this model. The gap height, bump deformation, bump contact area, and residual stresses after bonding can be estimated with this model. According to the simulation in this work, the best tactic for the flip chip Packaging Process using NCA is bonded at a lower temperature. This reduces the maximum warpage and only slightly decreases the average compressive residual stress in the bottom of bumps. A larger bonding force results in a larger bump contact area with the substrate, but has a lower compressive residual stress at the contact areas. The bonding force during the flip chip thermal bonding Process will affect the contact resistance and reliability of Packaging at the same time.
-
Development of a mathematical model for thermal-compression bonding of the COG Packaging Process using NCA
Microelectronics Reliability, 2011Co-Authors: Ching Ho Chang, Wen-bin YoungAbstract:In this decade, many new techniques have been introduced into the integrated circuit (IC) Packaging industry. Packaging technology used in liquid crystal displays (LCDs) has requirements related to critical issues such as high density interconnects, thinner Packaging size, and environmental safety. Driver IC chips are directly attached to LCD panels using flip chip technology with adhesives in the so called chip on glass (COG) Packaging Processes. To investigate the dependence of the bonding force on the bump deformation during Packaging, this study established a mathematical model to analyze COG Packaging Processes with non-conductive adhesives (NCAs). The plastic deformation of the bumps and the NCA flow between the chip and substrate are taken into account in this model. With this model, the contact resistance and the gap height after bonding can be estimated for different bonding force.
