The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
K.n. Tu - One of the best experts on this subject based on the ideXlab platform.
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Recent advances on kinetic analysis of solder joint reactions in 3D IC Packaging Technology
Materials Science and Engineering R: Reports, 2019Co-Authors: K.n. Tu, Yingxia LiuAbstract:We review five solder joint reactions in 3D IC Packaging Technology which are of wide interest: (1) Scallop-type growth of Cu 6 Sn 5 in solid-liquid interdiffusion reaction, (2) Whisker-type growth of Sn crystals at room temperature, (3) Layer-type intermetallic compound (IMC) growth in solid state aging, (4) Porous-type growth of Cu 3 Sn in μ-bumps, and (5) Pillar-type growth of Cu/Sn IMC down to 1 μm in diameter. The first two have been well covered in books and reviews on solder joint Technology, so only certain specific comments will be given here. On the other three, the layer-type IMC growth has been a long standing kinetic problem due to the extremely small concentration gradient across a stoichiometric IMC, but it has been resolved now, following Wagner's approach. The porous-type Cu 3 Sn was found in 2014. Kinetically, it is a complete cellular precipitation, containing a set of lamellar pores. It is rare because up to now all cellular precipitations are incomplete. The pillar-type Cu/Sn reactions down to 1 μm in diameter were carried out in 2016. Owing to a large surface/volume ratio, the reaction is controlled by surface diffusion, accompanied by interstitial diffusion of Cu in Sn.
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reliability challenges in 3d ic Packaging Technology
Microelectronics Reliability, 2011Co-Authors: K.n. TuAbstract:At the moment, a major paradigm change, from 2D IC to 3D IC, is occurring in microelectronic industry. Joule heating is serious in 3D IC, and vertical interconnect is the critical element to be developed. Also reliability concerns will be extremely important. For example, in order to remove heat, a temperature gradient must exist in the Packaging. If we assume just a difference of 1 °C across a micro-bump of 10 μm in diameter, the temperature gradient is 1000 °C/cm which cannot be ignored due to thermomigration. Equally challenging reliability issues are electromigration and stress-migration. Since the 3D IC structure is new, the details of reliability problems are mostly unknown. This paper presents a projection of the reliability challenges in 3D IC Packaging Technology on the basis of what we have known from flip chip Technology.
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reliability issues of pb free solder joints in electronic Packaging Technology
Electronic Components and Technology Conference, 2002Co-Authors: K.n. Tu, K. ZengAbstract:At present, the electronic Packaging industry is actively searching for Pb-free solders due to environmental concerns surrounding the Pb-containing solders. Due to the lack of reliability data, some electronics companies are reluctant to adopt Pb-free solders into their products. Hence, a review of the reliability issues of Pb-free solders is timely. We have selected three topics to be reviewed here. They are interfacial reaction between Pb-free solder and thin film under-bump metallization, electromigration in Pb-free flip chip solder joints, and Sn whisker growth on the Pb-free finish on a Cu leadframe.
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six cases of reliability study of pb free solder joints in electronic Packaging Technology
Materials Science & Engineering R-reports, 2002Co-Authors: K. Zeng, K.n. TuAbstract:Abstract Solder is widely used to connect chips to their Packaging substrates in flip chip Technology as well as in surface mount Technology. At present, the electronic Packaging industry is actively searching for Pb-free solders due to environmental concern of Pb-based solders. Concerning the reliability of Pb-free solders, some electronic companies are reluctant to adopt them into their high-end products. Hence, a review of the reliability behavior of Pb-free solders is timely. We use the format of “case study” to review six reliability problems of Pb-free solders in electronic Packaging Technology. We conducted analysis of these cases on the basis of thermodynamic driving force, time-dependent kinetic processes, and morphology and microstructure changes. We made a direct comparison to the similar problem in SnPb solder whenever it is available. Specifically, we reviewed: (1) interfacial reactions between Pb-free solder and thick metalliztion of bond-pad on the substrate-side, (2) interfacial reactions between Pb-free solder and thin-film under-bump metallization on the chip-side, (3) the growth of a layered intermetallic compound (IMC) by ripening in solid state aging of solder joints, (4) a long range interaction between chip-side and substrate-side metallizations across a solder joint, (5) electromigration in flip chip solder joints, and finally (6) Sn whisker growth on Pb-free finish on Cu leadframe. Perhaps, these cases may serve as helpful references to the understanding of other reliability behaviors of Pb-free solders.
S L Wright - One of the best experts on this subject based on the ideXlab platform.
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3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias
IEEE Journal of Solid-State Circuits, 2006Co-Authors: John U Knickerbocker, Chirag S Patel, Paul S Andry, Cornelia K Tsang, Edmund J Sprogis, R J Polastre, Leena Paivikki Buchwalter, Hua Gan, R. Horton, S L WrightAbstract:System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS Technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example. Silicon-on-silicon integration may include three-dimensional (3-D) integration on-chip or may leverage chip stacking or chip integration on package. Common Technology features include silicon through-vias, high-I/O interconnection and silicon-on-silicon either as 3-D integrated circuits, integrated chip stacks or silicon-on-silicon packages with passive function or high-bandwidth wiring. Silicon chips on silicon interposers with integrated function such as decoupling capacitors may provide a better module architecture compared to increased on-chip decoupling or off chip discrete capacitors mounted on package at the chip perimeter or underside of the package. Advanced silicon carrier package Technology with fine pitch (50 mum) interconnection is described. This silicon carrier package contains silicon through-vias and offers >16times increase over standard chip I/O, a 20times to 100times increase in wiring density over traditional organic and ceramic Packaging, and allows for integrated high-performance passives. Silicon carrier Technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers, silicon interposers with integrated decoupling capacitors, and mini-multi-chip modules (MMCMs) which integrate heterogeneous dies forming a single "virtual chip."
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three dimensional silicon integration using fine pitch interconnection silicon processing and silicon carrier Packaging Technology
Custom Integrated Circuits Conference, 2005Co-Authors: John U Knickerbocker, Chirag S Patel, Paul S Andry, Cornelia K Tsang, Paivikki L Buchwalter, Edmund J Sprogis, Raymond Robert Horton, R J Polastre, S L Wright, Christian SchusterAbstract:System-on-chip (SOC) and system-on-package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS Technology densities, a range of two and three dimensional silicon integration technologies are emerging which likely support next generation high-volume electronic applications and may serve high-performance computing applications. This paper discusses a few emerging technologies which offer opportunities for circuit integration on-chip as well as on-package using fine pitch interconnection, silicon wafer processing and silicon carrier Packaging Technology. Advanced silicon carrier package Technology with fine pitch (50/spl mu/m) interconnection is described. This silicon carrier package contains silicon through-vias and offers >16/spl times/ increase over standard chip I/O, a 20/spl times/ to 100/spl times/ increase in wiring density over traditional organic and ceramic Packaging, and allows for integrated high performance passives. Silicon carrier Technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers and mini-multi-chip modules (MMCM) which integrate heterogeneous dies forming a single "virtual chip".
Motohiro Fujiyoshi - One of the best experts on this subject based on the ideXlab platform.
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integration and Packaging Technology of mems on cmos capacitive tactile sensor for robot application using thick bcb isolation layer and backside grooved electrical connection
Sensors and Actuators A-physical, 2012Co-Authors: Mitsutoshi Makihata, Shuji Tanaka, Sakae Matsuzaki, Masanori Muroyama, Hitoshi Yamada, Takahiro Nakayama, Ui Yamaguchi, Kazuhiro Mima, Yutaka Nonomura, Motohiro FujiyoshiAbstract:Abstract This paper describes a novel wafer-level integration and Packaging Technology for a chip-size-packaged integrated tactile sensor. A MEMS wafer and a CMOS wafer were bonded with a thick (50 μm thick) BCB (benzocyclobutene) adhesive layer, and a capacitance gap for capacitive force sensor is formed between the wafers. The large thickness of BCB is advantageous to capacitively isolate the CMOS circuit and the capacitance electrodes. The thick BCB layer was formed on the CMOS wafer and molded with a glass mold to make a flat surface and via holes simultaneously. For surface mounting, bond pads are located on the backside of the sensor chip by drawing electrical feed lines through the chip edge. To make the feed lines in wafer level, tapered grooves were fabricated along the scribe lines by TMAH (tetramethyl ammonium hydroxide) wet etching, and half dicing was done along the grooves to access electrodes on the BEOL (back end of line) layer of the CMOS. Finally, the tactile sensor was completed and preliminarily evaluated.
S. Matsui - One of the best experts on this subject based on the ideXlab platform.
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three dimensional Packaging Technology for stacked dram with 3 gb s data transfer
IEEE Transactions on Electron Devices, 2008Co-Authors: M. Kawano, N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, S. MatsuiAbstract:A 3-D Packaging Technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire Packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) Technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability.
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A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer
2006 International Electron Devices Meeting, 2006Co-Authors: M. Kawano, S. Uchiyama, Y. Egawa, N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, S. Matsui, K. Shibata, J. YamadaAbstract:A 3D Packaging Technology has been developed for 4 Gbit DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire Packaging was carried out at the wafer level by using the so-called SMAFTI Technology. A new bump and wiring structure for feedthrough interposer (FTI) has also been developed for fine-pitch and low-cost bonding. Simulation of the transfer function of FTI wiring indicated a 3 Gbps/pin data transfer capability
J M Farber - One of the best experts on this subject based on the ideXlab platform.
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microbiological aspects of modified atmosphere Packaging Technology a review
Journal of Food Protection, 1991Co-Authors: J M FarberAbstract:Modified-atmosphere packaged (MAP) foods have become increasingly more common in North America, as food manufacturers have attempted to meet consumer demands for fresh, refrigerated foods with extended shelf life. Although much information exists in the general area of MAP Technology, research on the microbiological safety of these foods is still lacking. The great vulnerability of MAP foods from a safety standpoint is that with many modified atmospheres containing moderate to high levels of carbon dioxide, the aerobic spoilage organisms which usually warn consumers of spoilage are inhibited, while the growth of pathogens may be allowed or even stimulated. In the past, the major concerns have been the anaerobic pathogens, especially the psychrotrophic, nonproteolytic clostridia. However, because of the emergence of psychrotrophic pathogens such as Listeria monocytogenes, Aeromonas hydrophila, and Yersinia enterocolitica, new safety issues have been raised. This stems mainly from the fact that the extended...
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microbiological aspects of modified atmosphere Packaging Technology a review
Journal of Food Protection, 1991Co-Authors: J M FarberAbstract:Modified-atmosphere packaged (MAP) foods have become increasingly more common in North America, as food manufacturers have attempted to meet consumer demands for fresh, refrigerated foods with extended shelf life. Although much information exists in the general area of MAP Technology, research on the microbiological safety of these foods is still lacking. The great vulnerability of MAP foods from a safety standpoint is that with many modified atmospheres containing moderate to high levels of carbon dioxide, the aerobic spoilage organisms which usually warn consumers of spoilage are inhibited, while the growth of pathogens may be allowed or even stimulated. In the past, the major concerns have been the anaerobic pathogens, especially the psychrotrophic, nonproteolytic clostridia. However, because of the emergence of psychrotrophic pathogens such as Listeria monocytogenes , Aeromonas hydrophila , and Yersinia enterocolitica , new safety issues have been raised. This stems mainly from the fact that the extended shelf life of many MAP products may allow extra time for these pathogens to reach dangerously high levels in a food. This review focuses on the effects of MAP on the growth and survival of foodborne pathogens. Considered are the major psychrotrophic pathogens, the mesophiles such as the salmonellae and staphylococci, as well as the microaerophilic Campylobacter jejuni . The use of MAP in various food commodities such as beef, chicken, fish, and sandwiches is also discussed. Examples of various foods currently being packaged under MAP in North America are given, along with the specific atmospheres employed for the various food groups. Major safety concerns that still need to be addressed include the potential for growth and toxin production of Clostridium botulinum type E in MAP fish products, the growth of L. monocytogenes and A. hydrophila under modified atmospheres in various food commodities, and the enhanced survival of anaerobic spores and C. jejuni under certain gas atmospheres. Additional research with MAP foods is needed to ensure the microbiological safety of the numerous MAP products that will be available to the consumer in the next decade and beyond.
