The Experts below are selected from a list of 8211 Experts worldwide ranked by ideXlab platform
Daniel C. Frisbie - One of the best experts on this subject based on the ideXlab platform.
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Parasitic Capacitance effect on dynamic performance of aerosol jet printed sub 2 v poly 3 hexylthiophene electrolyte gated transistors
ACS Applied Materials & Interfaces, 2016Co-Authors: Fazel Zare Bidoky, Daniel C. FrisbieAbstract:Printed, low-voltage poly(3-hexylthiophene) (P3HT) electrolyte-gated transistors (EGTs) have favorable quasi-static characteristics, including sub 2 V operation, carrier mobility (μ) of 1 cm2/(V s), ON/OFF current ratio of 106, and static leakage current density of 10–6 A/cm2. Here we study the dynamic performance of P3HT EGTs in which the semiconductor, dielectric, and gate electrode were deposited using aerosol-jet printing; the source and drain electrodes were patterned by conventional microlithography. With a source-to-drain separation of 2.5 μm, the highest theoretical achievable switching frequency is ∼10 MHz, assuming the movement of charge through the semiconductor is the limiting step. However, the measured maximum switching frequency of P3HT EGTs to date is ∼1 kHz, implying that another process is slowing the response. By systematically varying the device geometry, we show that the frequency is limited by the Capacitance between the gate and drain (i.e., Parasitic Capacitance). The traditional s...
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Parasitic Capacitance Effect on Dynamic Performance of Aerosol-Jet-Printed Sub 2 V Poly(3-hexylthiophene) Electrolyte-Gated Transistors
2016Co-Authors: Fazel Zare Bidoky, Daniel C. FrisbieAbstract:Printed, low-voltage poly(3-hexylthiophene) (P3HT) electrolyte-gated transistors (EGTs) have favorable quasi-static characteristics, including sub 2 V operation, carrier mobility (μ) of 1 cm2/(V s), ON/OFF current ratio of 106, and static leakage current density of 10–6 A/cm2. Here we study the dynamic performance of P3HT EGTs in which the semiconductor, dielectric, and gate electrode were deposited using aerosol-jet printing; the source and drain electrodes were patterned by conventional microlithography. With a source-to-drain separation of 2.5 μm, the highest theoretical achievable switching frequency is ∼10 MHz, assuming the movement of charge through the semiconductor is the limiting step. However, the measured maximum switching frequency of P3HT EGTs to date is ∼1 kHz, implying that another process is slowing the response. By systematically varying the device geometry, we show that the frequency is limited by the Capacitance between the gate and drain (i.e., Parasitic Capacitance). The traditional scaling of switching time with the square of channel length (L) does not hold for P3HT EGTs. Rather, minimizing the size of the drain electrode increases the maximum switching speed. We achieve 10 kHz for P3HT EGTs with source/drain electrode dimensions of 2.5 μm × 50 μm and channel dimensions of 2.5 μm × 50 μm. Further improvements will require additional shrinkage of electrode dimensions as well as consideration of other factors such as ion gel thickness and carrier mobility
Fazel Zare Bidoky - One of the best experts on this subject based on the ideXlab platform.
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Parasitic Capacitance effect on dynamic performance of aerosol jet printed sub 2 v poly 3 hexylthiophene electrolyte gated transistors
ACS Applied Materials & Interfaces, 2016Co-Authors: Fazel Zare Bidoky, Daniel C. FrisbieAbstract:Printed, low-voltage poly(3-hexylthiophene) (P3HT) electrolyte-gated transistors (EGTs) have favorable quasi-static characteristics, including sub 2 V operation, carrier mobility (μ) of 1 cm2/(V s), ON/OFF current ratio of 106, and static leakage current density of 10–6 A/cm2. Here we study the dynamic performance of P3HT EGTs in which the semiconductor, dielectric, and gate electrode were deposited using aerosol-jet printing; the source and drain electrodes were patterned by conventional microlithography. With a source-to-drain separation of 2.5 μm, the highest theoretical achievable switching frequency is ∼10 MHz, assuming the movement of charge through the semiconductor is the limiting step. However, the measured maximum switching frequency of P3HT EGTs to date is ∼1 kHz, implying that another process is slowing the response. By systematically varying the device geometry, we show that the frequency is limited by the Capacitance between the gate and drain (i.e., Parasitic Capacitance). The traditional s...
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Parasitic Capacitance Effect on Dynamic Performance of Aerosol-Jet-Printed Sub 2 V Poly(3-hexylthiophene) Electrolyte-Gated Transistors
2016Co-Authors: Fazel Zare Bidoky, Daniel C. FrisbieAbstract:Printed, low-voltage poly(3-hexylthiophene) (P3HT) electrolyte-gated transistors (EGTs) have favorable quasi-static characteristics, including sub 2 V operation, carrier mobility (μ) of 1 cm2/(V s), ON/OFF current ratio of 106, and static leakage current density of 10–6 A/cm2. Here we study the dynamic performance of P3HT EGTs in which the semiconductor, dielectric, and gate electrode were deposited using aerosol-jet printing; the source and drain electrodes were patterned by conventional microlithography. With a source-to-drain separation of 2.5 μm, the highest theoretical achievable switching frequency is ∼10 MHz, assuming the movement of charge through the semiconductor is the limiting step. However, the measured maximum switching frequency of P3HT EGTs to date is ∼1 kHz, implying that another process is slowing the response. By systematically varying the device geometry, we show that the frequency is limited by the Capacitance between the gate and drain (i.e., Parasitic Capacitance). The traditional scaling of switching time with the square of channel length (L) does not hold for P3HT EGTs. Rather, minimizing the size of the drain electrode increases the maximum switching speed. We achieve 10 kHz for P3HT EGTs with source/drain electrode dimensions of 2.5 μm × 50 μm and channel dimensions of 2.5 μm × 50 μm. Further improvements will require additional shrinkage of electrode dimensions as well as consideration of other factors such as ion gel thickness and carrier mobility
Shuo Wang - One of the best experts on this subject based on the ideXlab platform.
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a generalized common mode current cancelation approach for power converters
IEEE Transactions on Industrial Electronics, 2015Co-Authors: Yongbin Chu, Shuo WangAbstract:The interwinding Parasitic Capacitance of transformers and the Parasitic Capacitance between semiconductor switches and the ground are two major contributors to the common-mode (CM) noise currents in switched mode power converters. In this paper, a generalized CM current cancelation approach is proposed for the reduction of CM noise in isolated power converters. The approach is demonstrated in a forward converter. In this approach, the total effect of the two Parasitic Capacitances on CM noise is represented with an equivalent Parasitic Capacitance (EPC) at low frequencies. With this EPC, different CM current cancelation techniques can be efficiently organized to simultaneously cancel the low-frequency CM noise caused by these two Parasitic Capacitances. Furthermore, the EPC can be used to evaluate and quantify the performance of CM noise reduction techniques. Both theoretical analysis and experimental results show that the proposed approach is easy to implement and can significantly attenuate low frequency CM noise and therefore greatly reduce CM filter size and cost.
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analysis and applications of Parasitic Capacitance cancellation techniques for emi suppression
IEEE Transactions on Industrial Electronics, 2010Co-Authors: Shuo Wang, F C LeeAbstract:This paper reviews and analyzes five Parasitic Capacitance cancellation methods. Critical parameters and constraints determining the cancellation frequency ranges are identified, and the effective frequency range for each cancellation method is derived based on these constraints. Due to these constraints, each method has specific advantages for certain applications. The cancellation techniques, which all make use of either mutual Capacitance or mutual inductance, are applied to different applications based on their advantages, and the experiments are carried out to verify the analysis.
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common mode noise reduction for power factor correction circuit with Parasitic Capacitance cancellation
IEEE Transactions on Electromagnetic Compatibility, 2007Co-Authors: Shuo WangAbstract:In this paper, a method using negative Capacitance to cancel the common-mode (CM) Parasitic Capacitance of boost power factor correction (PFC) converters is proposed. Both the theoretical analysis and experiments show that the proposed method is very easy to implement and very efficient to reduce CM noise.
Zhong Lin Wang - One of the best experts on this subject based on the ideXlab platform.
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structure and dimension effects on the performance of layered triboelectric nanogenerators in contact separation mode
ACS Nano, 2019Co-Authors: Linglin Zhou, Xinyuan Li, Chunlei Zhang, Ping Cheng, Weixing Song, Jie Wang, Zhong Lin WangAbstract:A triboelectric nanogenerator (TENG) is a potential solution for providing high output power by continuously harvesting ambient energy, which is expected to sustainably charge a battery for the new era—the era of the Internet of things and sensor networks. Generally, the existence of Parasitic Capacitance has been considered to be harmful in its output performance. Here, we systematically investigate the effects of structure and dimension of a TENG on its performance from the point view of Parasitic Capacitance by fabricating two types of layered TENGs with considering the dissimilarity of the two dielectric materials, symmetrical (ABBA) and alternate (ABAB) layered structure (SYM-TENG and ALT-TENG). Theoretical models of the two types of layered TENGs are proposed for illustrating their differences in Parasitic Capacitances and output characteristics. Larger Parasitic Capacitance enables the TENG to accommodate higher triboelectric charge density while reducing the internal impedance and maximum power de...
Mingdou Ker - One of the best experts on this subject based on the ideXlab platform.
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overview on esd protection designs of low Parasitic Capacitance for rf ics in cmos technologies
IEEE Transactions on Device and Materials Reliability, 2011Co-Authors: Mingdou Ker, Chunyu Lin, Yuanwen HsiaoAbstract:CMOS technology has been widely used to implement radio-frequency integrated circuits (RF ICs). However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of RF ICs. Therefore, on-chip ESD protection designs must be added at all input/output pads in RF circuits against ESD damages. To minimize the impacts from ESD protection circuit on RF performances, ESD protection circuit at input/output pads must be carefully designed. An overview on ESD protection designs with low Parasitic Capacitance for RF circuits in CMOS technology is presented in this paper. The comparisons among these ESD protection designs are also discussed. With the reduced Parasitic Capacitance, ESD protection circuit can be easily combined or co-designed with RF circuits. As the operating frequencies of RF circuits increase, on-chip ESD protection designs for RF applications will continuously be an important design task.
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modeling the Parasitic Capacitance of esd protection scr to co design matching network in rf ics
International Symposium on Next-Generation Electronics, 2010Co-Authors: Chunyu Lin, Mingdou KerAbstract:Silicon-controlled rectifier (SCR) has been reported with the good electrostatic discharge (ESD) robustness under the lower Parasitic Capacitance among ESD devices in CMOS technology. To correctly predict the performances of SCR-based ESD-protected RF circuit, it is essential for RF circuit design with accurate model of SCR device. The small-signal model of SCR in RF frequency band is proposed in this work. The measured Parasitic Capacitances well agree with the simulated Capacitances. With the proposed small-signal model, on-chip ESD protection can be co-designed with RF circuits to eliminate the negative impacts caused by ESD protection SCR on RF performances.
