The Experts below are selected from a list of 5799 Experts worldwide ranked by ideXlab platform
Jun-hyun Park - One of the best experts on this subject based on the ideXlab platform.
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empirical modeling and extraction of Parasitic Resistance in amorphous indium gallium zinc oxide thin film transistors
IEEE Transactions on Electron Devices, 2011Co-Authors: Jun-hyun Park, Hyun-kwang JungAbstract:We propose an extraction technique for Parasitic Resistance (RP) with L-, VGS-, and VDS-dependences even for large VDS in amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs), by employing IDS-VGS characteristics (as a function of VDS ) of two a-IGZO TFTs with different channel lengths ( L1 and L2 ). The Resistance between the source and drain is modeled as an effective total Resistance defined as RT* ≡ VDS/ID for all over the drain bias VDS including both linear and saturation regions. The proposed method can be efficiently employed to model dc I-V characteristics and extract the Parasitic Resistance in a-IGZO TFTs even with short channel lengths, because the internal drain voltage (VDS') is accurately calculated as a function of VGS, VDS, and L by deembedding the voltage drop across the Parasitic Resistance RP.
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Empirical Modeling and Extraction of Parasitic Resistance in Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors
IEEE Transactions on Electron Devices, 2011Co-Authors: Jun-hyun Park, Hyun-kwang JungAbstract:We propose an extraction technique for Parasitic Resistance (RP) with L-, VGS-, and VDS-dependences even for large VDS in amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs), by employing IDS-VGS characteristics (as a function of VDS ) of two a-IGZO TFTs with different channel lengths ( L1 and L2 ). The Resistance between the source and drain is modeled as an effective total Resistance defined as RT* ≡ VDS/ID for all over the drain bias VDS including both linear and saturation regions. The proposed method can be efficiently employed to model dc I-V characteristics and extract the Parasitic Resistance in a-IGZO TFTs even with short channel lengths, because the internal drain voltage (VDS') is accurately calculated as a function of VGS, VDS, and L by deembedding the voltage drop across the Parasitic Resistance RP.
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Surface-Potential-Based Analytic DC $I$ –$V$ Model With Effective Electron Density for $a$-IGZO TFTs Considering the Parasitic Resistance
IEEE Electron Device Letters, 2011Co-Authors: Jun-hyun ParkAbstract:A surface-potential-based analytic direct-current I -V model for amorphous indium-gallium-zinc-oxide thin-film transistors is proposed by adopting an effective electron density (neff) model for inclusion of both free carriers and localized charges in the channel. The proposed neff is efficient in reducing the error caused by neglecting the localized electron density nloc and allows a closed form of the analytic I-V model. The potential drop across the Parasitic Resistance RP in the source and drain regions is also fully considered in the model. Finally, we confirmed good agreement of the proposed model with measured IDS-VDS characteristics over a wide range of VGS and VDS.
Hyun-kwang Jung - One of the best experts on this subject based on the ideXlab platform.
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empirical modeling and extraction of Parasitic Resistance in amorphous indium gallium zinc oxide thin film transistors
IEEE Transactions on Electron Devices, 2011Co-Authors: Jun-hyun Park, Hyun-kwang JungAbstract:We propose an extraction technique for Parasitic Resistance (RP) with L-, VGS-, and VDS-dependences even for large VDS in amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs), by employing IDS-VGS characteristics (as a function of VDS ) of two a-IGZO TFTs with different channel lengths ( L1 and L2 ). The Resistance between the source and drain is modeled as an effective total Resistance defined as RT* ≡ VDS/ID for all over the drain bias VDS including both linear and saturation regions. The proposed method can be efficiently employed to model dc I-V characteristics and extract the Parasitic Resistance in a-IGZO TFTs even with short channel lengths, because the internal drain voltage (VDS') is accurately calculated as a function of VGS, VDS, and L by deembedding the voltage drop across the Parasitic Resistance RP.
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Empirical Modeling and Extraction of Parasitic Resistance in Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors
IEEE Transactions on Electron Devices, 2011Co-Authors: Jun-hyun Park, Hyun-kwang JungAbstract:We propose an extraction technique for Parasitic Resistance (RP) with L-, VGS-, and VDS-dependences even for large VDS in amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs), by employing IDS-VGS characteristics (as a function of VDS ) of two a-IGZO TFTs with different channel lengths ( L1 and L2 ). The Resistance between the source and drain is modeled as an effective total Resistance defined as RT* ≡ VDS/ID for all over the drain bias VDS including both linear and saturation regions. The proposed method can be efficiently employed to model dc I-V characteristics and extract the Parasitic Resistance in a-IGZO TFTs even with short channel lengths, because the internal drain voltage (VDS') is accurately calculated as a function of VGS, VDS, and L by deembedding the voltage drop across the Parasitic Resistance RP.
Toru Tanzawa - One of the best experts on this subject based on the ideXlab platform.
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Dickson charge pump circuit design with Parasitic Resistance in power lines
2009 IEEE International Symposium on Circuits and Systems, 2009Co-Authors: Toru TanzawaAbstract:Parasitic Resistance in power and ground lines is considered for Dickson charge pump circuit designs, and its equivalent model is modified for low voltage IC designs. When the optimization is done for maximized output current or for minimized rise time, it is not necessary to increase the number of stages, but it is necessary to increase the pumping capacitors. The impact of the Parasitic Resistance in addition to the Parasitic capacitance on charge pump circuit performances is discussed. The analytical results are compared with the SPICE simulation and the model has a sufficient accuracy within a typical error of 10%.
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ISCAS - Dickson charge pump circuit design with Parasitic Resistance in power lines
2009 IEEE International Symposium on Circuits and Systems, 2009Co-Authors: Toru TanzawaAbstract:Parasitic Resistance in power and ground lines is considered for Dickson charge pump circuit designs, and its equivalent model is modified for low voltage IC designs. When the optimization is done for maximized output current or for minimized rise time, it is not necessary to increase the number of stages, but it is necessary to increase the pumping capacitors. The impact of the Parasitic Resistance in addition to the Parasitic capacitance on charge pump circuit performances is discussed. The analytical results are compared with the SPICE simulation and the model has a sufficient accuracy within a typical error of 10%.
Matsuto Ogawa - One of the best experts on this subject based on the ideXlab platform.
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influence of source drain Parasitic Resistance on device performance of ultrathin body iii v channel metal oxide semiconductor field effect transistors
Applied Physics Express, 2011Co-Authors: Yōsuke Maegawa, Shunsuke Koba, Hideaki Tsuchiya, Matsuto OgawaAbstract:The influence of source/drain (S/D) Parasitic Resistance in ultrathin body (UTB) III–V channel metal–oxide–semiconductor field-effect transistor (MOSFET) was investigated based on Monte Carlo simulation. We found that heavily doped S/D improves source starvation and suppresses carrier's backscattering from drain to channel, owing to increased electron–electron scattering. As a result, the heavily doped S/D was shown to be effective to enhance the current drive and transconductance of UTB III–V channel MOSFET. In addition, we demonstrated that the heavily doped S/D has the advantage to provide unsaturated drain current characteristics.
Gerold W Neudeck - One of the best experts on this subject based on the ideXlab platform.
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an experimental study of the source drain Parasitic Resistance effects in amorphous silicon thin film transistors
Journal of Applied Physics, 1992Co-Authors: Shengwen Luan, Gerold W NeudeckAbstract:The effect of source/drain (S/D) Parasitic Resistance has been experimentally investigated for amorphous silicon (a‐Si:H) thin film transistors (TFTs). In general, the apparent field effect mobility decreases with decreasing channel length. However, the apparent threshold voltage is relatively constant. This may be attributed to an ohmic Parasitic Resistance due to the use of ion‐implanted n+ S/D regions. Self‐consistent results were obtained from both TFTs and from independent test structures for the TFT Parasitic Resistance, contact Resistance, and sheet Resistance. The results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total Parasitic Resistance. In this regard, both the S/D ion implantation and the S/D to gate overlap reduce the total Parasitic Resistance. Finally, the Parasitic Resistance is modeled as a gate voltage‐modulated channel Resistance, under the gate overlap, in series with a constant minimum contact Resistance.
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An experimental study of the source/drain Parasitic Resistance effects in amorphous silicon thin film transistors
Journal of Applied Physics, 1992Co-Authors: Shengwen Luan, Gerold W NeudeckAbstract:The effect of source/drain (S/D) Parasitic Resistance has been experimentally investigated for amorphous silicon (a‐Si:H) thin film transistors (TFTs). In general, the apparent field effect mobility decreases with decreasing channel length. However, the apparent threshold voltage is relatively constant. This may be attributed to an ohmic Parasitic Resistance due to the use of ion‐implanted n+ S/D regions. Self‐consistent results were obtained from both TFTs and from independent test structures for the TFT Parasitic Resistance, contact Resistance, and sheet Resistance. The results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total Parasitic Resistance. In this regard, both the S/D ion implantation and the S/D to gate overlap reduce the total Parasitic Resistance. Finally, the Parasitic Resistance is modeled as a gate voltage‐modulated channel Resistance, under the gate overlap, in series with a constant minimum contact Resistance.
