The Experts below are selected from a list of 18339 Experts worldwide ranked by ideXlab platform
Mark L Schattenburg - One of the best experts on this subject based on the ideXlab platform.
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development of a thermal oxide Patterning Method for mitigating coating stress induced distortion in silicon mirrors for the lynx x ray telescope mission concept conference presentation
Optics for EUV X-Ray and Gamma-Ray Astronomy IX, 2019Co-Authors: Youwei Yao, Brandon D Chalifoux, Ralf K Heilmann, Kaiwing Chan, Hideyuki Mori, Takashi Okajima, William W Zhang, Mark L SchattenburgAbstract:The thermal oxide Patterning Method has been proven effective for compensating coating stress on flat silicon wafers. In this paper we report progress of applying this Method on thin X-ray telescope silicon mirrors, produced by GSFC, which are 100 mm long, 0.5 mm thick, 30 degree in azimuthal span and 312 mm in radius of curvature (Wolter-I geometry). The mirrors’ front sides are sputter coated by 20 nm iridium layers which have ~-70 N/m compressive stress. Due to the difference in geometries, we developed a new FEA model to calculate the duty cycle in thermal oxide hexagon patterns to compensate the coating stress. In addition, a new fabrication process with customized photo lithographic tools has been developed to achieve optimum Patterning-precision on curved surfaces. Measurement results show that the developed Method can mitigate coating-induced distortion by a factor of ~4, corresponding to ~0.5 arc-second in RMS slope error. The residual surface error is dominated by mid-frequency ripples produced by the annealing process, which will be resolved in the future. The developed thermal oxide Patterning Method could be inexpensive and precise, which could be a candidate to resolve coating stress issues for the Lynx telescope in the future.
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progress of coating stress compensation of silicon mirrors for lynx x ray telescope mission concept using thermal oxide Patterning Method
Journal of Astronomical Telescopes Instruments and Systems, 2019Co-Authors: Brandon D Chalifoux, Ralf K Heilmann, Kaiwing Chan, Hideyuki Mori, Takashi Okajima, William W Zhang, Mark L SchattenburgAbstract:A thermal oxide Patterning Method has proven to be effective for correcting coating-stress-induced distortion on flat silicon wafers. We report progress on developing this Method for correcting curved silicon mirrors distorted by front-side iridium coatings. Owing to the difference in geometry, a finite element model has been established to calculate the appropriate duty cycle maps in thermal oxide hexagon patterns used for compensation. In addition, a photolithographic process, along with three-dimensional printed equipment, has been developed for creating patterns precisely on the back side of curved mirrors. The developed Method has been used to recover the original surface shape of two silicon mirrors which are 100-mm long, 0.5-mm thick, having 312-mm radius of curvature, and 30 deg in azimuthal span (Wolter-I geometry). These mirrors’ front sides are sputter-coated by 20-nm iridium layers with ∼-70 N / m integrated stress. Measurement results show that the developed Method can mitigate coating-induced distortion by a factor of ∼5 in RMS height and ∼4 in RMS slope error, corresponding to ∼0.5 arc sec RMS slope error. Residual errors after correction are dominated by mid-frequency ripples created during the annealing process, which will be resolved in the future. The presented Method is precise and inexpensive and a potential candidate for resolving the coating stress issue for Lynx optics in the future.
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thermal oxide Patterning Method for compensating coating stress in silicon substrates
Optics Express, 2019Co-Authors: Youwei Yao, Brandon D Chalifoux, Ralf K Heilmann, Mark L SchattenburgAbstract:We introduce a novel Method for correcting distortion in thin silicon substrates caused by coating stress. Thin substrates, such as lightweight mirrors for x-ray or optical imaging, and semiconductor wafers or flat panel substrates, are easily distorted by stress in thin film coatings. We report a new Method for correcting stress-induced distortion in flat silicon substrates which utilizes a micro-patterned silicon oxide layer on the back side of the substrate. Due to the excellent lithographic precision of the Patterning process, we demonstrate stress compensation control to a precision of ~0.2%. The proposed process is simple and inexpensive due to the relatively large pattern features on the photomask. The correction process has been tested on flat silicon wafers that were distorted by 30 nm-thick compressively-stressed coatings of chromium, achieving RMS surface height and slope error reductions of a factor of 68 and 50, respectively.
Ki Whan Song - One of the best experts on this subject based on the ideXlab platform.
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scalable 2 bit silicon oxide nitride oxide silicon sonos memory with physically separated local nitrides under a merged gate
Solid-state Electronics, 2004Co-Authors: Yongkyu Lee, Byung-gook Park, Ki Whan Song, Jong Duk Lee, Sung Taeg Kang, Jae Sung Sim, Suk Kang Sung, Chilhee Chung, Donggun Park, Kinam KimAbstract:A physically separated 2-bit SONOS memory with a single gate is fabricated for the first time. By forming physically separated 30-nm twin ONOs with an inverted sidewall spacer Patterning Method and damascene process under a merged-triple gate, the decrease of charge distribution and diffusion during and after CHEI (channel hot electron injection) program in 2-bit operation of the localized trap memory is observed in devices with the gate length of 90 nm. The inverted amorphous silicon spacer and the damascene gate process does not suffer from unit-cell size increase, lithographic resolution limit, and miss-alignment between gate and ONOs. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory (TSM) cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better 2-bit operation, endurance and retention than SSM, and absence of disturbance can be obtained in the short (sub 90 nm) gate length devices. � 2004 Elsevier Ltd. All rights reserved.
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twin sonos memory with 30 nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process
IEEE Electron Device Letters, 2004Co-Authors: Yongkyu Lee, Byung-gook Park, Ki Whan Song, Jae Woong Hyun, Jong Duk Lee, Sung Taeg Kang, Jeong Dong Choe, Sang Yeon Han, Jeong Nam Han, Sung Woo LeeAbstract:By manipulating the charge profile through the inverted sidewall Patterning on the channel, stable 2-bit operation in silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory with sub-90-nm gate length can be achieved. The fabricated memory cell has about 30-nm twin Oxide-Nitride-Oxide-Silicon physically separated by the inverted sidewall Patterning Method under the same control gate based on damascene gate process. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better endurance, retention, and erase speed than SSM can be obtained in the short (sub-100-nm) gate length devices.
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single electron transistors fabricated with sidewall spacer Patterning
Superlattices and Microstructures, 2003Co-Authors: Kyung Rok Kim, Ki Whan SongAbstract:Abstract We have implemented a sidewall spacer Patterning Method for novel dual-gate single-electron transistor (DGSET) and metal–oxide–semiconductor-based SET (MOSET) based on the uniform SOI wire, using conventional lithography and processing technology. A 30 nm wide silicon quantum wire is defined by a sidewall spacer Patterning Method, and depletion gates for two tunnel junctions of the DGSET are formed by the doped polycrystalline silicon sidewall. The fabricated DGSET and MOSET show clear single-electron tunneling phenomena at liquid nitrogen temperature and insensitivity of the Coulomb oscillation period to gate bias conditions. On the basis of the phase control capability of the sidewall depletion gates, we have proposed a complementary self-biasing Method, which enables the SET/CMOS hybrid multi-valued logic (MVL) to operate perfectly well at high temperature, where the peak-to-valley current ratio of Coulomb oscillation severely decreases. The suggested scheme is evaluated by SPICE simulation with an analytical DGSET model, and it is confirmed that even DGSETs with a large Si island can be utilized efficiently in the multi-valued logic.
Yongkyu Lee - One of the best experts on this subject based on the ideXlab platform.
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scalable 2 bit silicon oxide nitride oxide silicon sonos memory with physically separated local nitrides under a merged gate
Solid-state Electronics, 2004Co-Authors: Yongkyu Lee, Byung-gook Park, Ki Whan Song, Jong Duk Lee, Sung Taeg Kang, Jae Sung Sim, Suk Kang Sung, Chilhee Chung, Donggun Park, Kinam KimAbstract:A physically separated 2-bit SONOS memory with a single gate is fabricated for the first time. By forming physically separated 30-nm twin ONOs with an inverted sidewall spacer Patterning Method and damascene process under a merged-triple gate, the decrease of charge distribution and diffusion during and after CHEI (channel hot electron injection) program in 2-bit operation of the localized trap memory is observed in devices with the gate length of 90 nm. The inverted amorphous silicon spacer and the damascene gate process does not suffer from unit-cell size increase, lithographic resolution limit, and miss-alignment between gate and ONOs. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory (TSM) cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better 2-bit operation, endurance and retention than SSM, and absence of disturbance can be obtained in the short (sub 90 nm) gate length devices. � 2004 Elsevier Ltd. All rights reserved.
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twin sonos memory with 30 nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process
IEEE Electron Device Letters, 2004Co-Authors: Yongkyu Lee, Byung-gook Park, Ki Whan Song, Jae Woong Hyun, Jong Duk Lee, Sung Taeg Kang, Jeong Dong Choe, Sang Yeon Han, Jeong Nam Han, Sung Woo LeeAbstract:By manipulating the charge profile through the inverted sidewall Patterning on the channel, stable 2-bit operation in silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory with sub-90-nm gate length can be achieved. The fabricated memory cell has about 30-nm twin Oxide-Nitride-Oxide-Silicon physically separated by the inverted sidewall Patterning Method under the same control gate based on damascene gate process. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better endurance, retention, and erase speed than SSM can be obtained in the short (sub-100-nm) gate length devices.
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excellent 2 bit silicon oxide nitride oxide silicon sonos memory tsm with a 90 nm merged triple gate
International Semiconductor Device Research Symposium, 2003Co-Authors: Yongkyu Lee, Byung-gook Park, Jong Duk Lee, Sung Taeg Kang, Jae Sung Sim, Suk Kang Sung, Tae Hoon Kim, Chilhee Chung, Donggun Park, Kyungwan KimAbstract:For the breakthrough of scaling limit, simple structure memories are developed and also multi-bit operation memories are introduced concurrently. A new TSM-ISP cell which has 30 nm local twin SONOS memory separated by the inverted sidewall Patterning Method under the 90 nm merged-triple gate. This new cell structure provides perfect 2-bit program, excellent endurance, erase characteristics and retention compared with the conventional single ONO type SONOS in the sub-90-nm regime.
Stuart Wenham - One of the best experts on this subject based on the ideXlab platform.
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Evolution of metal plating for silicon solar cell metallisation
Progress in Photovoltaics: Research and Applications, 2013Co-Authors: Alison Lennon, Yu Yao, Stuart WenhamAbstract:Increasingsilverpricesandreducingsiliconwaferthicknessesprovideincentivesforsiliconsolarcellmanufacturingtodevelop new metallisation strategies that do not rely on screen printing and preferably reduce silver usage. Recently, metal plating has re-emerged as a metallisation process that may address these future requirements. This paper reports on the evolution of metal plating techniques, from their use in early silicon solar cells, to current light-induced plating processes. Unlike screen-printed metallisation, metal plating typically requires an initial Patterning step to create openings in a masking layer for the subsequent self-aligned metallisation. Consequently, relevant recently-developed dielectric Patterning Methods are also reviewed because, in many cases, the plating process must be adapted to the properties of the Patterning Method used. The potential of new light-induced plating processes to form cost-effective copper metallisation is supported by the recent activity in the develop- ment of metal plating tools for commercial silicon solar cell manufacture. Copyright © 2012 John Wiley & Sons, Ltd.
Youwei Yao - One of the best experts on this subject based on the ideXlab platform.
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development of a thermal oxide Patterning Method for mitigating coating stress induced distortion in silicon mirrors for the lynx x ray telescope mission concept conference presentation
Optics for EUV X-Ray and Gamma-Ray Astronomy IX, 2019Co-Authors: Youwei Yao, Brandon D Chalifoux, Ralf K Heilmann, Kaiwing Chan, Hideyuki Mori, Takashi Okajima, William W Zhang, Mark L SchattenburgAbstract:The thermal oxide Patterning Method has been proven effective for compensating coating stress on flat silicon wafers. In this paper we report progress of applying this Method on thin X-ray telescope silicon mirrors, produced by GSFC, which are 100 mm long, 0.5 mm thick, 30 degree in azimuthal span and 312 mm in radius of curvature (Wolter-I geometry). The mirrors’ front sides are sputter coated by 20 nm iridium layers which have ~-70 N/m compressive stress. Due to the difference in geometries, we developed a new FEA model to calculate the duty cycle in thermal oxide hexagon patterns to compensate the coating stress. In addition, a new fabrication process with customized photo lithographic tools has been developed to achieve optimum Patterning-precision on curved surfaces. Measurement results show that the developed Method can mitigate coating-induced distortion by a factor of ~4, corresponding to ~0.5 arc-second in RMS slope error. The residual surface error is dominated by mid-frequency ripples produced by the annealing process, which will be resolved in the future. The developed thermal oxide Patterning Method could be inexpensive and precise, which could be a candidate to resolve coating stress issues for the Lynx telescope in the future.
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thermal oxide Patterning Method for compensating coating stress in silicon substrates
Optics Express, 2019Co-Authors: Youwei Yao, Brandon D Chalifoux, Ralf K Heilmann, Mark L SchattenburgAbstract:We introduce a novel Method for correcting distortion in thin silicon substrates caused by coating stress. Thin substrates, such as lightweight mirrors for x-ray or optical imaging, and semiconductor wafers or flat panel substrates, are easily distorted by stress in thin film coatings. We report a new Method for correcting stress-induced distortion in flat silicon substrates which utilizes a micro-patterned silicon oxide layer on the back side of the substrate. Due to the excellent lithographic precision of the Patterning process, we demonstrate stress compensation control to a precision of ~0.2%. The proposed process is simple and inexpensive due to the relatively large pattern features on the photomask. The correction process has been tested on flat silicon wafers that were distorted by 30 nm-thick compressively-stressed coatings of chromium, achieving RMS surface height and slope error reductions of a factor of 68 and 50, respectively.