The Experts below are selected from a list of 291 Experts worldwide ranked by ideXlab platform

E.g. Friedman - One of the best experts on this subject based on the ideXlab platform.

  • Effect of shield insertion on reducing crosstalk Noise between coupled interconnects
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: Junmou Zhang, E.g. Friedman
    Abstract:

    Placing shields around a victim signal line is a common way to enhance signal integrity while minimizing delay uncertainty. For two coupled interconnects with a shield between the lines, the coupling Noise can produce a Peak Noise of 15% of V/sub dd/ in a 0.18 /spl mu/m CMOS technology. A pseudo-2/spl pi/ RC model is used to develop an analytic estimate of the Peak Noise for shielded interconnects. The Peak Noise model is accurate within an average error of 4.4% as compared to SPICE. The effects of the shield width, length, separation between the shield and the signal, and the number of connections tieing the shield to ground on the overall crosstalk Noise are described in this paper. Based on the Peak Noise model, a minimum number of ground connections for a target shield line with Noise constraints is obtained. Inserting a shield line between two coupled interconnects is shown to be more effective in reducing crosstalk Noise than increasing the physical separation.

  • Crosstalk Noise model for shielded interconnects in VLSI-based circuits
    IEEE International [Systems-on-Chip] SOC Conference 2003. Proceedings., 2003
    Co-Authors: Junmou Zhang, E.g. Friedman
    Abstract:

    Placing shields around a victim signal line is a common way to enhance signal integrity while minimizing delay uncertainty. An analytic model of the Peak Noise is developed for shielded interconnects, based on a pseudo-2/spl pi/ RC model. A design methodology for inserting shields between coupled interconnects, to reduce crosstalk Noise, is presented.

  • ISCAS (1) - Peak Noise prediction in loosely coupled interconnect [VLSI circuits]
    ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999
    Co-Authors: K.t. Tang, E.g. Friedman
    Abstract:

    Interconnect in VLSI circuits is best modeled as a lossy transmission line in high speed integrated circuits. Analytical expressions for the coupling Noise between adjacent interconnect are presented to estimate the Peak Noise voltage on a quiet line based on the assumption that these interconnections are loosely coupled, where the effect of the coupling Noise on the waveform of an active line is small. These closed form expressions are also applied to the condition of a varying load impedance. The estimated error of the Peak Noise amplitude at the near end of the quiet line is less than 15% under high loss and non-matching load conditions.

  • Peak Noise prediction in loosely coupled interconnect [VLSI circuits]
    1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999
    Co-Authors: K.t. Tang, E.g. Friedman
    Abstract:

    Interconnect in VLSI circuits is best modeled as a lossy transmission line in high speed integrated circuits. Analytical expressions for the coupling Noise between adjacent interconnect are presented to estimate the Peak Noise voltage on a quiet line based on the assumption that these interconnections are loosely coupled, where the effect of the coupling Noise on the waveform of an active line is small. These closed form expressions are also applied to the condition of a varying load impedance. The estimated error of the Peak Noise amplitude at the near end of the quiet line is less than 15% under high loss and non-matching load conditions.

Chenming Hu - One of the best experts on this subject based on the ideXlab platform.

  • Accurate in situ measurement of Peak Noise and delay change induced by interconnect coupling
    IEEE Journal of Solid-State Circuits, 2001
    Co-Authors: T. Sato, D. Sylvester, Chenming Hu
    Abstract:

    An accurate in situ Noise and delay measurement technique that considers interconnect coupling effects is presented. This paper improves upon previous work by proposing (1) a novel accurate Peak detector to measure on-chip crosstalk Noise, and (2) in situ measurement structure to characterize the dynamic delay effect. A test chip was fabricated using 0.35-/spl mu/m process and measured results demonstrate the effectiveness of the proposed technique. Noise Peak measurements show 40-60 mV (1.8% average) accuracy to simulation results and dynamic delay change curve match well with SPICE. The proposed measurement technique can be used for interconnect model verification and calibration, and has applications to various design automation tools such as Noise-aware static timing analysis.

  • ICCAD - Effects of global interconnect optimizations on performance estimation of deep submicron design
    IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 2000
    Co-Authors: Chenming Hu, A.b. Kahng, S. Muddu, Xuejue Huang, D. Stroobandt, D. Sylvester
    Abstract:

    In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, Peak Noise, delay uncertainty due to Noise, power, and cost. In doing so, we develop a new system-performance simulation model as a set of studies within the MARCO GSRC Technology Extrapolation (GTX) system. We model a typical point-to-point global interconnect and focus on accurate assessment of both circuit and design technology with respect to such issues as inductance, signal line shielding, dynamic delay, buffer placement uncertainty and repeater staggering. We demonstrate, for example, that optimal wire sizing models need to consider inductive effects -- and that use of more accurate {-1,3} worst-case capacitive coupling Noise switch factors substantially increases Peak Noise estimates compared to traditional {0,2} bounds. We also find that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energy-delay issues.

  • Accurate in-situ measurement of Peak Noise and signal delay induced by interconnect coupling
    2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056), 2000
    Co-Authors: T. Sato, D. Sylvester, Chenming Hu
    Abstract:

    In deep submicron processes, inaccuracy of interconnect models can lead to serious design errors. New circuit performance measurement schemes are necessary to verify and calibrate the interconnect models. An accurate in-situ Noise and delay measurement technique is developed and a test chip is fabricated to demonstrate its efficacy. The proposed technique can experimentally characterize the Noise Peak height and the timing skew due to Noise. It is intended for generating circuit design guidelines and verifying CAD models and tools.

  • Effects of global interconnect optimizations on performance estimation of deep submicron design
    IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 2000
    Co-Authors: Chenming Hu, Xuejue Huang, A.b. Kahng, S. Muddu, D. Stroobandt, D. Sylvester
    Abstract:

    In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, Peak Noise, delay uncertainty due to Noise, power, and cost. In doing so, we develop a new system-performance simulation model as a set of studies within the MARCO GSRC Technology Extrapolation (GTX) system. We model a typical point-to-point global interconnect and focus on accurate assessment of both circuit and design technology with respect to such issues as inductance, signal line shielding, dynamic delay, buffer placement uncertainty and repeater staggering. We demonstrate, for example, that optimal wire sizing models need to consider inductive effects-and that use of more accurate (-1,3) worst-case capacitive coupling Noise switch factors substantially increases Peak Noise estimates compared to traditional (0,2) bounds. We also find that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energy-delay issues.

D. Sylvester - One of the best experts on this subject based on the ideXlab platform.

  • Accurate in situ measurement of Peak Noise and delay change induced by interconnect coupling
    IEEE Journal of Solid-State Circuits, 2001
    Co-Authors: T. Sato, D. Sylvester, Chenming Hu
    Abstract:

    An accurate in situ Noise and delay measurement technique that considers interconnect coupling effects is presented. This paper improves upon previous work by proposing (1) a novel accurate Peak detector to measure on-chip crosstalk Noise, and (2) in situ measurement structure to characterize the dynamic delay effect. A test chip was fabricated using 0.35-/spl mu/m process and measured results demonstrate the effectiveness of the proposed technique. Noise Peak measurements show 40-60 mV (1.8% average) accuracy to simulation results and dynamic delay change curve match well with SPICE. The proposed measurement technique can be used for interconnect model verification and calibration, and has applications to various design automation tools such as Noise-aware static timing analysis.

  • Accurate in-situ measurement of Peak Noise and signal delay induced by interconnect coupling
    2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056), 2000
    Co-Authors: T. Sato, D. Sylvester, Chenming Hu
    Abstract:

    In deep submicron processes, inaccuracy of interconnect models can lead to serious design errors. New circuit performance measurement schemes are necessary to verify and calibrate the interconnect models. An accurate in-situ Noise and delay measurement technique is developed and a test chip is fabricated to demonstrate its efficacy. The proposed technique can experimentally characterize the Noise Peak height and the timing skew due to Noise. It is intended for generating circuit design guidelines and verifying CAD models and tools.

  • Effects of global interconnect optimizations on performance estimation of deep submicron design
    IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 2000
    Co-Authors: Chenming Hu, Xuejue Huang, A.b. Kahng, S. Muddu, D. Stroobandt, D. Sylvester
    Abstract:

    In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, Peak Noise, delay uncertainty due to Noise, power, and cost. In doing so, we develop a new system-performance simulation model as a set of studies within the MARCO GSRC Technology Extrapolation (GTX) system. We model a typical point-to-point global interconnect and focus on accurate assessment of both circuit and design technology with respect to such issues as inductance, signal line shielding, dynamic delay, buffer placement uncertainty and repeater staggering. We demonstrate, for example, that optimal wire sizing models need to consider inductive effects-and that use of more accurate (-1,3) worst-case capacitive coupling Noise switch factors substantially increases Peak Noise estimates compared to traditional (0,2) bounds. We also find that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energy-delay issues.

Junmou Zhang - One of the best experts on this subject based on the ideXlab platform.

  • Effect of shield insertion on reducing crosstalk Noise between coupled interconnects
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: Junmou Zhang, E.g. Friedman
    Abstract:

    Placing shields around a victim signal line is a common way to enhance signal integrity while minimizing delay uncertainty. For two coupled interconnects with a shield between the lines, the coupling Noise can produce a Peak Noise of 15% of V/sub dd/ in a 0.18 /spl mu/m CMOS technology. A pseudo-2/spl pi/ RC model is used to develop an analytic estimate of the Peak Noise for shielded interconnects. The Peak Noise model is accurate within an average error of 4.4% as compared to SPICE. The effects of the shield width, length, separation between the shield and the signal, and the number of connections tieing the shield to ground on the overall crosstalk Noise are described in this paper. Based on the Peak Noise model, a minimum number of ground connections for a target shield line with Noise constraints is obtained. Inserting a shield line between two coupled interconnects is shown to be more effective in reducing crosstalk Noise than increasing the physical separation.

  • ISCAS (2) - Effect of shield insertion on reducing crosstalk Noise between coupled interconnects
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: Junmou Zhang, Eby G. Friedman
    Abstract:

    Placing shields around a victim signal line is a common way to enhance signal integrity while minimizing delay uncertainty. For two coupled interconnects with a shield between the lines, the coupling Noise can produce a Peak Noise of 15% of V/sub dd/ in a 0.18 /spl mu/m CMOS technology. A pseudo-2/spl pi/ RC model is used to develop an analytic estimate of the Peak Noise for shielded interconnects. The Peak Noise model is accurate within an average error of 4.4% as compared to SPICE. The effects of the shield width, length, separation between the shield and the signal, and the number of connections tieing the shield to ground on the overall crosstalk Noise are described in this paper. Based on the Peak Noise model, a minimum number of ground connections for a target shield line with Noise constraints is obtained. Inserting a shield line between two coupled interconnects is shown to be more effective in reducing crosstalk Noise than increasing the physical separation.

  • Crosstalk Noise model for shielded interconnects in VLSI-based circuits
    IEEE International [Systems-on-Chip] SOC Conference 2003. Proceedings., 2003
    Co-Authors: Junmou Zhang, E.g. Friedman
    Abstract:

    Placing shields around a victim signal line is a common way to enhance signal integrity while minimizing delay uncertainty. An analytic model of the Peak Noise is developed for shielded interconnects, based on a pseudo-2/spl pi/ RC model. A design methodology for inserting shields between coupled interconnects, to reduce crosstalk Noise, is presented.

T. Sato - One of the best experts on this subject based on the ideXlab platform.

  • Accurate in situ measurement of Peak Noise and delay change induced by interconnect coupling
    IEEE Journal of Solid-State Circuits, 2001
    Co-Authors: T. Sato, D. Sylvester, Chenming Hu
    Abstract:

    An accurate in situ Noise and delay measurement technique that considers interconnect coupling effects is presented. This paper improves upon previous work by proposing (1) a novel accurate Peak detector to measure on-chip crosstalk Noise, and (2) in situ measurement structure to characterize the dynamic delay effect. A test chip was fabricated using 0.35-/spl mu/m process and measured results demonstrate the effectiveness of the proposed technique. Noise Peak measurements show 40-60 mV (1.8% average) accuracy to simulation results and dynamic delay change curve match well with SPICE. The proposed measurement technique can be used for interconnect model verification and calibration, and has applications to various design automation tools such as Noise-aware static timing analysis.

  • Accurate in-situ measurement of Peak Noise and signal delay induced by interconnect coupling
    2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056), 2000
    Co-Authors: T. Sato, D. Sylvester, Chenming Hu
    Abstract:

    In deep submicron processes, inaccuracy of interconnect models can lead to serious design errors. New circuit performance measurement schemes are necessary to verify and calibrate the interconnect models. An accurate in-situ Noise and delay measurement technique is developed and a test chip is fabricated to demonstrate its efficacy. The proposed technique can experimentally characterize the Noise Peak height and the timing skew due to Noise. It is intended for generating circuit design guidelines and verifying CAD models and tools.