The Experts below are selected from a list of 14226 Experts worldwide ranked by ideXlab platform
Gabriel M. Rebeiz - One of the best experts on this subject based on the ideXlab platform.
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Ka-Band SiGe HBT Low Phase Imbalance Differential 3-Bit Variable Gain LNA
IEEE Microwave and Wireless Components Letters, 2008Co-Authors: Byungwook Min, Gabriel M. RebeizAbstract:This letter presents the design and implementation of a differential Ka-band variable gain low noise amplifier (VG-LNA) with low insertion Phase Imbalance. The VG-LNA is based on a 0.12 mum SiGe heterojunction bipolar transistor process, and the gain variation is achieved using bias current steering. The measured VG-LNA gain at 32-34 GHz is 9-20 dB with eight different linear-in-magnitude gain states, and with a noise figure of 3.4-4.3 dB. The measured rms Phase Imbalance is < 2.5deg at 26-40 GHz for all gain states and this is achieved using a novel compensating resistor in the bias network. The VG-LNA consumes 33 mW (13.5 mA, 2.5 V) and the input 1-dB gain compression point is -27 dBm. The chip size is 0.13 mm2 without pads.
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A 10–50-GHz CMOS Distributed Step Attenuator With Low Loss and Low Phase Imbalance
IEEE Journal of Solid-state Circuits, 2007Co-Authors: Byungwook Min, Gabriel M. RebeizAbstract:This paper presents the design and measurement of a 10-50-GHz low-loss distributed CMOS step attenuator with low Phase Imbalance. The attenuation is controlled by 12 nMOS varistors, and the nMOS parasitics are absorbed in a synthetic transmission line to result in a wide bandwidth. The electrical distance between the varistors is explored to minimize the size of the distributed attenuator, and a method to balance the insertion Phase is presented. At 33-37 GHz, the minimum attenuation state loss is 2.1 dB, and the maximum attenuation state loss is 13.0 dB. The attenuator has a maximum attenuation range of 11 dB with 0.9-dB steps (13 states). The rms Phase Imbalance is less than 3 at DC-50 GHz for all attenuation states. The attenuator does not consume any static power and the input 1-dB compression point is 5 dBm (defined as the 1-dB drop in the maximum attenuation range) at 20 GHz. The total chip size excluding pads is 200750 (0.15).
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a 10 50 ghz cmos distributed step attenuator with low loss and low Phase Imbalance
IEEE Journal of Solid-state Circuits, 2007Co-Authors: Byungwook Min, Gabriel M. RebeizAbstract:This paper presents the design and measurement of a 10-50-GHz low-loss distributed CMOS step attenuator with low Phase Imbalance. The attenuation is controlled by 12 nMOS varistors, and the nMOS parasitics are absorbed in a synthetic transmission line to result in a wide bandwidth. The electrical distance between the varistors is explored to minimize the size of the distributed attenuator, and a method to balance the insertion Phase is presented. At 33-37 GHz, the minimum attenuation state loss is 2.1 dB, and the maximum attenuation state loss is 13.0 dB. The attenuator has a maximum attenuation range of 11 dB with 0.9-dB steps (13 states). The rms Phase Imbalance is less than 3 at DC-50 GHz for all attenuation states. The attenuator does not consume any static power and the input 1-dB compression point is 5 dBm (defined as the 1-dB drop in the maximum attenuation range) at 20 GHz. The total chip size excluding pads is 200750 (0.15).
Byungwook Min - One of the best experts on this subject based on the ideXlab platform.
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v w band cmos distributed step attenuator with low Phase Imbalance
IEEE Microwave and Wireless Components Letters, 2014Co-Authors: Kyung Won Kim, Hyo Sung Lee, Byungwook MinAbstract:This letter presents a high power V-W band CMOS distributed step attenuator with a low Phase Imbalance. Thirteen nMOS varistors are periodically placed in a t-line and change the attenuation in a step up to 10 dB. For high power handling, four-stacked and biased nMOS transistors are used for the varistor. Shunt t-lines under the varistors compensate for the Phase Imbalance of the attenuation states. The total chip size is 0.38 mm 2 excluding pads. The insertion loss of the attenuator is 5.6-11.2 dB at 50-110 GHz. The return loss is <;-15 dB at 50-110 GHz with the rms Phase Imbalance of <;1.4° and the input 1 dB compression point of 17 dBm.
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V-W Band CMOS Distributed Step Attenuator With low Phase Imbalance
IEEE Microwave and Wireless Components Letters, 2014Co-Authors: Kyung Won Kim, Hyo Sung Lee, Byungwook MinAbstract:This letter presents a high power V-W band CMOS distributed step attenuator with a low Phase Imbalance. Thirteen nMOS varistors are periodically placed in a t-line and change the attenuation in a step up to 10 dB. For high power handling, four-stacked and biased nMOS transistors are used for the varistor. Shunt t-lines under the varistors compensate for the Phase Imbalance of the attenuation states. The total chip size is 0.38 mm 2 excluding pads. The insertion loss of the attenuator is 5.6-11.2 dB at 50-110 GHz. The return loss is
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Ka-Band SiGe HBT Low Phase Imbalance Differential 3-Bit Variable Gain LNA
IEEE Microwave and Wireless Components Letters, 2008Co-Authors: Byungwook Min, Gabriel M. RebeizAbstract:This letter presents the design and implementation of a differential Ka-band variable gain low noise amplifier (VG-LNA) with low insertion Phase Imbalance. The VG-LNA is based on a 0.12 mum SiGe heterojunction bipolar transistor process, and the gain variation is achieved using bias current steering. The measured VG-LNA gain at 32-34 GHz is 9-20 dB with eight different linear-in-magnitude gain states, and with a noise figure of 3.4-4.3 dB. The measured rms Phase Imbalance is < 2.5deg at 26-40 GHz for all gain states and this is achieved using a novel compensating resistor in the bias network. The VG-LNA consumes 33 mW (13.5 mA, 2.5 V) and the input 1-dB gain compression point is -27 dBm. The chip size is 0.13 mm2 without pads.
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A 10–50-GHz CMOS Distributed Step Attenuator With Low Loss and Low Phase Imbalance
IEEE Journal of Solid-state Circuits, 2007Co-Authors: Byungwook Min, Gabriel M. RebeizAbstract:This paper presents the design and measurement of a 10-50-GHz low-loss distributed CMOS step attenuator with low Phase Imbalance. The attenuation is controlled by 12 nMOS varistors, and the nMOS parasitics are absorbed in a synthetic transmission line to result in a wide bandwidth. The electrical distance between the varistors is explored to minimize the size of the distributed attenuator, and a method to balance the insertion Phase is presented. At 33-37 GHz, the minimum attenuation state loss is 2.1 dB, and the maximum attenuation state loss is 13.0 dB. The attenuator has a maximum attenuation range of 11 dB with 0.9-dB steps (13 states). The rms Phase Imbalance is less than 3 at DC-50 GHz for all attenuation states. The attenuator does not consume any static power and the input 1-dB compression point is 5 dBm (defined as the 1-dB drop in the maximum attenuation range) at 20 GHz. The total chip size excluding pads is 200750 (0.15).
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a 10 50 ghz cmos distributed step attenuator with low loss and low Phase Imbalance
IEEE Journal of Solid-state Circuits, 2007Co-Authors: Byungwook Min, Gabriel M. RebeizAbstract:This paper presents the design and measurement of a 10-50-GHz low-loss distributed CMOS step attenuator with low Phase Imbalance. The attenuation is controlled by 12 nMOS varistors, and the nMOS parasitics are absorbed in a synthetic transmission line to result in a wide bandwidth. The electrical distance between the varistors is explored to minimize the size of the distributed attenuator, and a method to balance the insertion Phase is presented. At 33-37 GHz, the minimum attenuation state loss is 2.1 dB, and the maximum attenuation state loss is 13.0 dB. The attenuator has a maximum attenuation range of 11 dB with 0.9-dB steps (13 states). The rms Phase Imbalance is less than 3 at DC-50 GHz for all attenuation states. The attenuator does not consume any static power and the input 1-dB compression point is 5 dBm (defined as the 1-dB drop in the maximum attenuation range) at 20 GHz. The total chip size excluding pads is 200750 (0.15).
Xinping Huang - One of the best experts on this subject based on the ideXlab platform.
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gain Phase Imbalance and dc offset compensation in quadrature modulators
International Symposium on Circuits and Systems, 2002Co-Authors: Xinping Huang, M CaronAbstract:This paper describes a technique to estimate gain and Phase Imbalances and DC offsets in a quadrature modulator and to pre-compensate the in-Phase and quadrature signals, so that image suppression is maximized and LO leakage is minimized at the modulator output. To validate the technique, an experiment with two 2.5 GHz direct modulators was conducted, and the results show that both the image suppression and LO leakage can be improved by at least 20 dB.
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ISCAS (4) - Gain/Phase Imbalance and DC offset compensation in quadrature modulators
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002Co-Authors: Xinping Huang, M CaronAbstract:This paper describes a technique to estimate gain and Phase Imbalances and DC offsets in a quadrature modulator and to pre-compensate the in-Phase and quadrature signals, so that image suppression is maximized and LO leakage is minimized at the modulator output. To validate the technique, an experiment with two 2.5 GHz direct modulators was conducted, and the results show that both the image suppression and LO leakage can be improved by at least 20 dB.
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a recursive gram schmidt orthonormalization procedure and its application to communications
International Workshop on Signal Processing Advances in Wireless Communications, 2001Co-Authors: Xinping Huang, M Caron, D HindsonAbstract:This paper presents a recursive Gram-Schmidt orthonormalization procedure. It employs adders and multipliers only, and it is very suitable and efficient for real-time high-speed DSP implementations. Its usefulness to communications is illustrated through the gain and Phase Imbalance compensation in a coherent QPSK receiver. Computer simulation shows that the bit error rate performance of the QPSK receiver is improved significantly after compensating the gain and Phase Imbalances by using the recursive Gram-Schmidt orthonormalization procedure.
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On transmitter gain/Phase Imbalance compensation at receiver
IEEE Communications Letters, 2000Co-Authors: Xinping HuangAbstract:This letter explores the benefits of compensating for transmitter gain and Phase Imbalances in a receiver for quadrature communication systems. It is assumed that the gain and Phase Imbalances are introduced at the transmitter only. The Gram-Schmidt orthogonalization procedure is used at the receiver to compensate for the Imbalances. Computer simulation has been performed to study a coherent differential QPSK communication system. It has been found that the bit error rate performance is improved significantly if the transmitter Phase Imbalance is compensated for. However, no improvement can be obtained if the transmitter gain Imbalance is compensated for.
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on transmitter gain Phase Imbalance compensation at receiver
IEEE Communications Letters, 2000Co-Authors: Xinping HuangAbstract:This letter explores the benefits of compensating for transmitter gain and Phase Imbalances in a receiver for quadrature communication systems. It is assumed that the gain and Phase Imbalances are introduced at the transmitter only. The Gram-Schmidt orthogonalization procedure is used at the receiver to compensate for the Imbalances. Computer simulation has been performed to study a coherent differential QPSK communication system. It has been found that the bit error rate performance is improved significantly if the transmitter Phase Imbalance is compensated for. However, no improvement can be obtained if the transmitter gain Imbalance is compensated for.
A.-a. Edris - One of the best experts on this subject based on the ideXlab platform.
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Impact of Imbalanced Phase operation of SSSC on damping subsynchronous resonance
2011 IEEE Power and Energy Society General Meeting, 2011Co-Authors: D. Rai, G. Ramakrishna, Sherif O. Faried, A.-a. EdrisAbstract:The paper investigates the impact of using Static Synchronous Series Compensator (SSSC) in Phase Imbalanced operation modes on damping subsynchronous resonance in series capacitive compensated transmission grid. Phase Imbalance has the potential of reducing the energy exchange between the electrical and mechanical sides of the turbine-generator and, therefore, damps subsynchronous oscillations. The validity and effectiveness of different proposed Phase Imbalanced modes have been demonstrated on the IEEE first benchmark model by means of time domain simulation analysis using the EMTP-RV program.
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Enhancement of power system dynamics using a Phase Imbalanced series compensation scheme
IEEE PES General Meeting, 2010Co-Authors: D. Rai, G. Ramakrishna, Sherif O. Faried, A.-a. EdrisAbstract:The paper presents a new series capacitive compensation concept, which enhances power system dynamics. The idea behind the concept is a series capacitive compensation which provides balanced compensation at the power frequency while it results in Phase Imbalance at other frequency of oscillations. The compensation scheme is a combination of a single-Phase Thyristor Controlled Series Capacitor (TCSC) and fixed series capacitors in series in one Phase of the compensated transmission line and fixed capacitors on the other two Phases.
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A Novel Approach for Damping Subsynchronous Resonance Using a STATCOM
2008Co-Authors: D. Rai, G. Ramakrishna, A.-a. EdrisAbstract:This paper investigates the impact of a STATCOM operating in a Phase Imbalanced mode on damping subsynchronous resonance in series capacitive compensated transmission grid. Phase Imbalance has the potential of reducing the energy exchange between the electrical and mechanical sides of turbine-generator and, therefore, damps the subsynchronous oscillations resulting from series capacitive compensation. The effectiveness of the proposed scheme is demonstrated on the IEEE first benchmark model by means of time domain simulations using the EMTP-RV program.
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Subsynchronous resonance countermeasure using Phase Imbalance
IEEE Transactions on Power Systems, 1993Co-Authors: A.-a. EdrisAbstract:Since the discovery in 1970 that subsynchronous resonance (SSR) was the main cause of the shaft failures at the Mohave plant in Southern Nevada, extensive research and development efforts have been devoted to the development of effective SSR mitigation measures. This paper presents a contribution to these efforts by providing a new concept for simple and reliable SSR mitigation. The basic idea is to reduce the energy exchange between the two sides of turbine-generator sets at subsynchronous oscillations by weakening the electromechanical coupling. This is attained by creating Phase Imbalance at subsynchronous oscillations. The Imbalance diminishes the capability of the three Phase currents to develop interacting electromagnetic torques and, therefore, suppresses energy exchange between the electrical and mechanical sides of turbine-generator sets. The objective of this paper is to study the influence of having the Phase Imbalance associated with the generator to be protected from potential torsional interaction problems. >
K. Araki - One of the best experts on this subject based on the ideXlab platform.
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Gain/Phase Imbalance compensation for multi-band quadrature receivers
IEEE 60th Vehicular Technology Conference 2004. VTC2004-Fall. 2004, 2004Co-Authors: T. Nakagawa, Munehiro Matsui, K. ArakiAbstract:This paper presents a compensation technique for the gain/Phase Imbalance of quadrature demodulators for direct conversion receivers. The power measurements for the Imbalance estimation can be done in less than ten symbol periods of the test signals. This means that the compensation method does not need many iterative cycles using the least mean square method or discrete Fourier transform that previous methods need. Experimental results show that the differences between the estimated and actual values are small: the gain Imbalance was 0.3 dB, and the Phase Imbalance was 1.1/spl deg/.
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gain Phase Imbalance compensation for multi band quadrature receivers
Vehicular Technology Conference, 2004Co-Authors: T. Nakagawa, Munehiro Matsui, K. ArakiAbstract:This paper presents a compensation technique for the gain/Phase Imbalance of quadrature demodulators for direct conversion receivers. The power measurements for the Imbalance estimation can be done in less than ten symbol periods of the test signals. This means that the compensation method does not need many iterative cycles using the least mean square method or discrete Fourier transform that previous methods need. Experimental results show that the differences between the estimated and actual values are small: the gain Imbalance was 0.3 dB, and the Phase Imbalance was 1.1/spl deg/.