The Experts below are selected from a list of 24 Experts worldwide ranked by ideXlab platform

Shiyan Hu - One of the best experts on this subject based on the ideXlab platform.

  • ISVLSI - Buffering Single-Walled Carbon Nanotubes Bundle Interconnects for Timing Optimization
    2014 IEEE Computer Society Annual Symposium on VLSI, 2014
    Co-Authors: Yuchen Zhou, Shiyan Hu
    Abstract:

    As prevailing copper interconnect technology advances to its fundamental Physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization. Single-walled carbon nanotubes (SWCNTs) bundle interconnects have emerged as a promising replacement material for copper interconnects due to their superior conductivity. Previous works have focused on studying device and interconnect modeling for bundled SWCNTs while none of them consider deployment of such an advanced technology into VLSI Physical Design. To the best of the authors' knowledge, this paper develops the first Physical Design Technique for the interconnect optimization using carbon nanotube interconnects. We propose a timing driven buffer insertion Technique for bundled SWCNTs, where the standard buffering algorithm has been enhanced to accommodate some features in the SWCNT timing modelling. Our experimental results on a set of scaled industrial nets at 22nm technology demonstrate that compared to copper buffering, CNT buffering can save over 50% buffer area with the same timing constraint. In addition, CNT buffering can effectively reduce the delay by up to 32%. Further, CNT buffering runs in time similar to copper buffering.

  • Buffering single-walled carbon nanotubes bundle interconnects for timing optimization
    Proceedings of IEEE Computer Society Annual Symposium on VLSI ISVLSI, 2014
    Co-Authors: Lin Liu, Yuchen Zhou, Shiyan Hu
    Abstract:

    © 2014 IEEE.As prevailing copper interconnect technology advances to its fundamental Physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization. Single-walled carbon nanotubes (SWCNTs) bundle interconnects have emerged as a promising replacement material for copper interconnects due to their superior conductivity. Previous works have focused on studying device and interconnect modeling for bundled SWCNTs while none of them consider deployment of such an advanced technology into VLSI Physical Design. To the best of the authors' knowledge, this paper develops the first Physical Design Technique for the interconnect optimization using carbon nanotube interconnects. We propose a timing driven buffer insertion Technique for bundled SWCNTs, where the standard buffering algorithm has been enhanced to accommodate some features in the SWCNT timing modelling. Our experimental results on a set of scaled industrial nets at 22nm technology demonstrate that compared to copper buffering, CNT buffering can save over 50% buffer area with the same timing constraint. In addition, CNT buffering can effectively reduce the delay by up to 32%. Further, CNT buffering runs in time similar to copper buffering.

Yuchen Zhou - One of the best experts on this subject based on the ideXlab platform.

  • ISVLSI - Buffering Single-Walled Carbon Nanotubes Bundle Interconnects for Timing Optimization
    2014 IEEE Computer Society Annual Symposium on VLSI, 2014
    Co-Authors: Yuchen Zhou, Shiyan Hu
    Abstract:

    As prevailing copper interconnect technology advances to its fundamental Physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization. Single-walled carbon nanotubes (SWCNTs) bundle interconnects have emerged as a promising replacement material for copper interconnects due to their superior conductivity. Previous works have focused on studying device and interconnect modeling for bundled SWCNTs while none of them consider deployment of such an advanced technology into VLSI Physical Design. To the best of the authors' knowledge, this paper develops the first Physical Design Technique for the interconnect optimization using carbon nanotube interconnects. We propose a timing driven buffer insertion Technique for bundled SWCNTs, where the standard buffering algorithm has been enhanced to accommodate some features in the SWCNT timing modelling. Our experimental results on a set of scaled industrial nets at 22nm technology demonstrate that compared to copper buffering, CNT buffering can save over 50% buffer area with the same timing constraint. In addition, CNT buffering can effectively reduce the delay by up to 32%. Further, CNT buffering runs in time similar to copper buffering.

  • Buffering single-walled carbon nanotubes bundle interconnects for timing optimization
    Proceedings of IEEE Computer Society Annual Symposium on VLSI ISVLSI, 2014
    Co-Authors: Lin Liu, Yuchen Zhou, Shiyan Hu
    Abstract:

    © 2014 IEEE.As prevailing copper interconnect technology advances to its fundamental Physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization. Single-walled carbon nanotubes (SWCNTs) bundle interconnects have emerged as a promising replacement material for copper interconnects due to their superior conductivity. Previous works have focused on studying device and interconnect modeling for bundled SWCNTs while none of them consider deployment of such an advanced technology into VLSI Physical Design. To the best of the authors' knowledge, this paper develops the first Physical Design Technique for the interconnect optimization using carbon nanotube interconnects. We propose a timing driven buffer insertion Technique for bundled SWCNTs, where the standard buffering algorithm has been enhanced to accommodate some features in the SWCNT timing modelling. Our experimental results on a set of scaled industrial nets at 22nm technology demonstrate that compared to copper buffering, CNT buffering can save over 50% buffer area with the same timing constraint. In addition, CNT buffering can effectively reduce the delay by up to 32%. Further, CNT buffering runs in time similar to copper buffering.

Lin Liu - One of the best experts on this subject based on the ideXlab platform.

  • Buffering single-walled carbon nanotubes bundle interconnects for timing optimization
    Proceedings of IEEE Computer Society Annual Symposium on VLSI ISVLSI, 2014
    Co-Authors: Lin Liu, Yuchen Zhou, Shiyan Hu
    Abstract:

    © 2014 IEEE.As prevailing copper interconnect technology advances to its fundamental Physical limit, interconnect delay due to ever-increasing wire resistivity has greatly limited the circuit miniaturization. Single-walled carbon nanotubes (SWCNTs) bundle interconnects have emerged as a promising replacement material for copper interconnects due to their superior conductivity. Previous works have focused on studying device and interconnect modeling for bundled SWCNTs while none of them consider deployment of such an advanced technology into VLSI Physical Design. To the best of the authors' knowledge, this paper develops the first Physical Design Technique for the interconnect optimization using carbon nanotube interconnects. We propose a timing driven buffer insertion Technique for bundled SWCNTs, where the standard buffering algorithm has been enhanced to accommodate some features in the SWCNT timing modelling. Our experimental results on a set of scaled industrial nets at 22nm technology demonstrate that compared to copper buffering, CNT buffering can save over 50% buffer area with the same timing constraint. In addition, CNT buffering can effectively reduce the delay by up to 32%. Further, CNT buffering runs in time similar to copper buffering.

Morteza Saheb Zamani - One of the best experts on this subject based on the ideXlab platform.

  • metro on chip an efficient Physical Design Technique for congestion reduction
    IEICE Electronics Express, 2007
    Co-Authors: Ali Jahanian, Morteza Saheb Zamani
    Abstract:

    Routing congestion is one of the main factors in Designing in deep submicron technology that may cause unroutability of the Design, signal integrity problems and large delays in detoured wires. In this paper, a new methodology is presented which multiplexes regular nets by asynchronous serial transceivers in the Physical Design flow in order to improve the congestion of the Design. Experimental results show that for the attempted benchmarks, the overflow congestion was reduced by up to 40.03% without any degradation in clock frequency and negligible power consumption overhead.

Ali Jahanian - One of the best experts on this subject based on the ideXlab platform.

  • metro on chip an efficient Physical Design Technique for congestion reduction
    IEICE Electronics Express, 2007
    Co-Authors: Ali Jahanian, Morteza Saheb Zamani
    Abstract:

    Routing congestion is one of the main factors in Designing in deep submicron technology that may cause unroutability of the Design, signal integrity problems and large delays in detoured wires. In this paper, a new methodology is presented which multiplexes regular nets by asynchronous serial transceivers in the Physical Design flow in order to improve the congestion of the Design. Experimental results show that for the attempted benchmarks, the overflow congestion was reduced by up to 40.03% without any degradation in clock frequency and negligible power consumption overhead.