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Antonio Gonzalez - One of the best experts on this subject based on the ideXlab platform.
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merlin exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment
International Symposium on Computer Architecture, 2017Co-Authors: Manolis Kaliorakis, Dimitris Gizopoulos, Ramon Canal, Antonio GonzalezAbstract:Early reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural structures modeled in performance simulators is an accurate method to measure their Architectural Vulnerability Factor (AVF) but requires excessively long campaigns to obtain high statistical significance. We propose MeRLiN1, a methodology to boost microarchitecture level injection-based reliability assessment by several orders of magnitude and keep the accuracy of the assessment unaffected even for large injection campaigns with very high statistical significance. The core of MeRLiN is the grouping of faults of an initial list in equivalent classes. All faults in the same group target equivalent vulnerable intervals of program execution ending up to the same static instruction that reads the faulty entries. Faults in the same group occur in different times and entries of a structure and it is extremely likely that they all have the same effect in program execution; thus, fault injection is performed only on a few representatives from each group. We evaluate MeRLiN for different sizes of the Physical Register file, the store queue and the first level data cache of a contemporary microarchitecture running MiBench and SPEC CPU2006 benchmarks. For all our experiments, MeRLiN is from 2 to 3 orders of magnitude faster than an extremely high statistical significant injection campaign, reporting the same reliability measurements with negligible loss of accuracy. Finally, we theoretically analyze MeRLiN's statistical behavior to further justify its accuracy.
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leveraging Register windows to reduce Physical Registers to the bare minimum
IEEE Transactions on Computers, 2010Co-Authors: Eduardo Quinones, Joanmanuel Parcerisa, Antonio GonzalezAbstract:Register window is an architectural technique that reduces memory operations required to save and restore Registers across procedure calls. Its effectiveness depends on the size of the Register file. Such Register requirements are normally increased for out-of-order execution because it requires Registers for the in-flight instructions, in addition to the architectural ones. However, a large Register file has an important cost in terms of area and power and may even affect the cycle time. In this paper, we propose a software/hardware early Register release technique that leverage Register windows to drastically reduce the Register requirements, and hence, reduce the Register file cost. Contrary to the common belief that out-of-order processors with Register windows would need a large Physical Register file, this paper shows that the Physical Register file size may be reduced to the bare minimum by using this novel microarchitecture. Moreover, our proposal has much lower hardware complexity than previous approaches, and requires minimal changes to a conventional Register window scheme. Performance studies show that the proposed technique can reduce the number of Physical Registers to the number of logical Registers plus one (minimum number to guarantee forward progress) and still achieve almost the same performance as an unbounded Register file.
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Dynamic Register Renaming through Virtual-Physical Registers
2000Co-Authors: Teresa Monreal, Antonio Gonzalez, Victor Vinals, Mateo Valero, Jose Gonzalez, Zaragoza SpainAbstract:Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper present a novel dynamic Register renaming scheme that delays the allocation of Physical Registers until a late stage in the pipeline. We show that it can provide important savings in number of Physical Registers so it can significantly shorter the Register file access time. Delaying the allocation of Physical Registers requires some artifact to keep track of dependences. This is achieved by introducing the concept of virtual-Physical Registers, which are tags that do not require any storage location. The proposed renaming scheme shortens the average number of cycles that each Physical Register is allocated, and allows for an early execution of instructions since they can obtain a Physical Register for its destination earlier than with the conventional sc..
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Dynamic Register Renaming through Virtual-Physical Registers
2000Co-Authors: Teresa Monreal, Antonio Gonzalez, Mateo Valero, Jose Gonzalez, Victor VinalsAbstract:Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper present a novel dynamic Register renaming scheme that delays the allocation of Physical Registers until a late stage in the pipeline. We show that it can provide important savings in number of Physical Registers so it can significantly shorter the Register file access time. Delaying the allocation of Physical Registers requires some artifact to keep track of dependences. This is achieved by introducing the concept of virtual-Physical Registers, which are tags that do not require any storage location. The proposed renaming scheme shortens the average number of cycles that each Physical Register is allocated, and allows for an early execution of instructions since they can obtain a Physical Register for its destination earlier than with the conventional scheme. Early execution is especially beneficial for branches and memory operations, since the former can be resolved earlier and the latter can prefetch their data in advance
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delaying Physical Register allocation through virtual Physical Registers
International Symposium on Microarchitecture, 1999Co-Authors: Teresa Monreal, Antonio Gonzalez, Mateo Valero, Jose Gonzalez, Victor VinalsAbstract:Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper present a novel Physical Register management scheme that allows for a late allocation (at the end of execution) of Registers. We show that it can provide significant savings in number of Registers and thus, it can significantly shorter the Register file access time. The approach is based on virtual-Physical Registers, which we presented in a previous work, extended with a new Register allocation policy. This policy consists of an on-demand allocation in order to maximize the Register usage, combined with a stealing mechanism that prevents older instruction from being delayed by younger ones. This shortens the average number of cycles that each Physical Register is allocated, and allows for an early execution of instructions since they can obtain a Physical Register for its destination earlier than with the conventional scheme. Early execution is especially beneficial for branches and memory operations, since the former can be resolved earlier and the latter can prefetch their data in advance.
Mateo Valero - One of the best experts on this subject based on the ideXlab platform.
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Exploiting Inactive Rename Slots for Detecting Soft Errors
2012Co-Authors: Mehmet Kayaalp, Oguz Ergin, Osman S. Ünsal, Mateo ValeroAbstract:Abstract. Register renaming is a widely used technique to remove false data dependencies in superscalar datapaths. Rename logic consists of a table that holds a Physical Register mapping for each architectural Register and a logic for checking intra-group dependencies. This logic checking consists of a number of comparators that compares the values of destination and source Registers. Previous research has shown that the full capacity of the dependency checking logic is not used at each cycle. In this paper we propose some techniques that make use of the unused capacity of the dependency checking logic of the rename stage in order to detect soft errors that occur on the Register tags while the instructions are passing through the frontend of the processor
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Exploiting the Dependency Checking Logic of the Rename Stage for Soft Error Detection
2010Co-Authors: Oguz Ergin, Osman S. Ünsal, Gülay Yalçın, Mateo ValeroAbstract:Abstract. Register renaming is a widely used technique to remove false data dependencies in superscalar datapaths. Rename logic consists of a table that holds a Physical Register mapping for each architectural Register and a logic for checking intra-group dependencies which consists of a number of comparators that compares the values of destination and source Registers. Previous research has shown that the full capacity of the dependency checking logic is not used at each cycle. In this paper we propose a technique that makes use of the unused capacity of the dependency checking logic of the rename stage in order to detect soft errors that occur on the Register tags while the instructions are passing through the frontend of the processor.
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selection of the Register file size and the resource allocation policy on smt processors
Symposium on Computer Architecture and High Performance Computing, 2008Co-Authors: Jesus Alastruey, Teresa Monreal, Francisco J Cazorla, Victor Vinals, Mateo ValeroAbstract:The performance impact of the Physical Register File(PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared resource. In this paper we analyze the effect on performance of the PRF size for a broad set of resource allocation policies (Icount, Stall, Flush, Flush++, Static,Dcra and Hill-climbing) and evaluate them under two metrics: instructions per second (IPS) for throughput and harmonic mean of weighted IPCs (Hmean-wIPC) for fairness. We have found that resource allocation policy and PRF size should be considered together in order to obtain the best score in the proposed metrics. For instance, for the analyzed 2 and 4-threaded SPEC CPU2000 workloads,small PRFs are best managed by Flush, whereas for larger PRFs, Hill-climbing and Static lead to the best values for the throughput and fairness metrics, respectively.The second contribution of this work is a simple procedure that, for a given resource allocation policy, selects the PRF size that maximizes IPS and obtains for Hmean-wIPC a value close to its maximum. According to our results, Hill-climbing with a 320-entry PRF achieves the best figures for 2-threaded workloads. When executing 4-threaded workloads, Hill-Climbing with a 384-entry PRF achieves the best throughput whereas Static obtains the best throughput-fairness balance.
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Microarchitectural Support for Speculative Register Renaming
2007 IEEE International Parallel and Distributed Processing Symposium, 2007Co-Authors: Jesus Alastruey, Teresa Monreal, Victor Vinals, Mateo ValeroAbstract:This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission of Physical Register allocation along with the speculative early release of Physical Registers. These renaming policies may cause a Register operand not to be kept in the Physical Register file (PRF). Thus, we add a low-ported auxiliary Register file (XRF) located outside the processor core that keeps the values absent in PRF and supplies them at higher latency. To support the location of Register operands being either in PRF or XRF, we use virtual Registers. We consider omission and release policies directed by hardware prediction. Namely, we use a single last-use predictor that directs both speculative omission and release. We call this mechanism SR-LUP (speculative renaming based on last-use prediction). Two last-use predictor designs of incremental complexity and performance are analyzed. In a 256-ROB, 8-way processor with an 80int+80fp PRF, SR-LUP with an 11-port 256int+256fp XRF, speeds up computations up to 11.5% and 29% for INT and FP SPEC2K benchmarks, respectively. For FP benchmarks, if the PRF limits the clock frequency, a conventionally managed 128int+128fp PRF can be replaced using SR-LUP by a 64int+64fp PRF backed up with a 10-port 224int+224fp XRF, showing 19% IPS gain.
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Late Allocation and Early Release of Physical Registers
2004Co-Authors: Teresa Monreal, Ieee Computer Society, Mateo ValeroAbstract:Abstract—The Register File is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the size and number of ports of the Register file. In conventional Register renaming schemes, both Register allocation and releasing are conservatively done, the former at the rename stage, before Registers are loaded with values, and the latter at the commit stage of the instruction redefining the same Register, once Registers are not used anymore. In this paper, we introduce VP-LAER, a renaming scheme that allocates Registers later and releases them earlier than conventional schemes. Specifically, Physical Registers are allocated at the end of the execution stage and released as soon as the processor realizes that there will be no further use of them. VP-LAER enhances Register utilization, that is, the fraction of allocated Registers having a value to be read in the future. Detailed cycle-level simulations show either a significant speedup for a given Register file size or a reduction in the Register file size for a given performance level, especially for floating-point codes, where the Register file pressure is usually high. Index Terms—Register renaming, out-of-order processors, Register file optimization, Physical Register allocation and releasing, precise exceptions.
Dmitry Ponomarev - One of the best experts on this subject based on the ideXlab platform.
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Register versioning a low complexity implementation of Register renaming in out of order microarchitectures
International Conference on Parallel Processing, 2009Co-Authors: Hui Zeng, Kanad Ghose, Dmitry PonomarevAbstract:Register renaming and associated Register management mechanisms represent a significant source of complexity in out-of-order micro architectures. We propose the use of Register versioning to simplify this logic. Hardware-supported Register versioning permits monotonically increasing version numbers to uniquely identify each uncommitted instance of an architectural Register. Register versioning replaces the Physical Register file with a simpler structure that integrates the Physical Register file with an architectural Register file, both having the same number of entries, namely the number of architectural Registers. The integrated structure uses local bitcell level connections to commit results to a precise state, saving a significant amount of energy in the process. We also propose optimizations to the proposed mechanism. Despite drastic data path simplification, our proposed architecture performs within 6% of traditional out-of-order processors and within 4% of the performance of a SMT processor with 4 threads.
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address value decoupling for early Register deallocation
International Conference on Parallel Processing, 2006Co-Authors: Deniz Balkan, Dmitry Ponomarev, Joseph Sharkey, Aneesh AggarwalAbstract:We propose a series of aggressive Register deallocation mechanisms to reduce the Register file pressure and increase the parallelism exploited by superscalar microprocessors. Our techniques are based on a key observation that a Register value can be temporarily decoupled from the Register identifier. Specifically, even if a Physical Register is deallocated, the value is still available in the Register and can be read by the dependent instructions until the Register is overwritten. In these situations, we can effectively overlap the consumption of the produced Register value and partial processing of the instruction that gets the same Register reassigned to it. In this paper, we propose several realizations of the address-value decoupling idea and discuss their implications on the performance. Our most aggressive scheme achieves an average IPC speedup of 14.6% across simulated SPEC 2000 benchmarks.
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Register packing exploiting narrow width operands for reducing Register file pressure
International Symposium on Microarchitecture, 2004Co-Authors: Oguz Ergin, Kanad Ghose, Deniz Balkan, Dmitry PonomarevAbstract:A large percentage of computed results have fewer significant bits compared to the full width of a Register. We exploit this fact to pack multiple results into a single Physical Register to reduce the pressure on the Register file in a superscalar processor. Two schemes for dynamically packing multiple "narrow-width" results into partitions within a single Register are evaluated. The first scheme is conservative and allocates a full-width Register for a computed result. If the computed result turns out to be narrow, the result is reallocated to partitions within a common Register, freeing up the full-width Register. The second scheme allocates Register partitions based on a prediction of the width of the result and reallocates Register partitions when the actual result width is higher than what was predicted. If the actual width is narrower than what was predicted, allocated partitions are freed up. A detailed evaluation of our schemes show that average IPC gains of up to 15% can be realized across the SPEC 2000 benchmarks on a somewhat Register-constrained datapath.
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Register packing exploiting narrow width operands for reducing Register file pressure
International Symposium on Microarchitecture, 2004Co-Authors: Oguz Ergin, Kanad Ghose, Deniz Balkan, Dmitry PonomarevAbstract:A large percentage of computed results have fewer significant bits compared to the full width of a Register. We exploit this fact to pack multiple results into a single Physical Register to reduce the pressure on the Register file in a superscalar processor. Two schemes for dynamically packing multiple "narrow-width" results into partitions within a single Register are evaluated. The first scheme is conservative and allocates a full-width Register for a computed result. If the computed result turns out to be narrow, the result is reallocated to partitions within a common Register, freeing up the full-width Register. The second scheme allocates Register partitions based on a prediction of the width of the result and reallocates Register partitions when the actual result width is higher than what was predicted. If the actual width is narrower than what was predicted, allocated partitions are freed up. A detailed evaluation of our schemes show that average IPC gains of up to 15% can be realized across the SPEC 2000 benchmarks on a somewhat Register-constrained datapath.
Amir Roth - One of the best experts on this subject based on the ideXlab platform.
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Three Extensions To Register Integration
2013Co-Authors: Amir Roth, Vlad Petric, Anne BracyAbstract:Register integration (or just integration) is a Register renaming discipline that implements instruction reuse via Physical Register sharing. Initially developed to perform squash reuse, the integration mechanism is a powerful reuse tool that can exploit more reuse scenarios. In this paper; we describe three extensions to the initial integration mechanism that expand its applicability and boost its performance impact. First, we extend squash reuse to general reuse. Whereas squash reuse maintains the superscalar concept of an instruction instance "owning " its outputPhysical Register; we allow multiple instructions to simultaneously and seamlessly share a single Physical Register. Next, we replace the PC-indexing scheme used by squash reuse with an opcode-based indexing scheme that exposes more integration opportunities. Finally, we introduce an extension called reverse integration in which we speculatively create integration entries for the inverses of operations-for instance, when renaming an add, we create an entry for the inverse subtract. Reverse integration allows us to reuse operations that were not specijied by the original program. We use reverse integration to obtain a free implementation of speculative memory bypassing for stack-pointer based loads (Register fills and restores). Our evaluation shows that these extensions increase the integration rate-the number of retired instructions that integrate older results and bypass the execution engine-to an average of 17 % on the SPEC2000 intege
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Flexible Register Management using Reference Counting
2012Co-Authors: Steven Battle, Andrew D. Hilton, Mark Hempstead, Amir RothAbstract:Conventional out-of-order processors that use a unified Physical Register file allocate and reclaim Registers explicitly using a free list that operates as a circular queue. We describe and evaluate a more flexible Register management scheme—reference counting. We implement reference counting using a bit-matrix with a column for every Physical Register and a row for every entity that can hold a Physical Register, e.g., an in-flight instruction. Columns are NOR’ed together to create a bitvector free list from which Registers are allocated using priority encoders. We describe reference counting designs that support micro-architectural techniques including Register file power gating, dynamic Register move elimination, Register file checkpointing, and latency tolerant execution. Performance and circuit simulation show that the energy cost of reference counting is low and is easily recouped by the savings of the techniques it enables. 1
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CPROB: Checkpoint Processing with Opportunistic Minimal Recovery
2010Co-Authors: Andrew Hilton, Neeraj Eswaran, Amir RothAbstract:is a Physical Register management scheme that supports a larger instruction window and higher average IPC than conventional ROB-style Register management. It does so by restricting mis-speculation recovery to checkpoints created at rename, and leveraging this restriction to aggressively reclaim Registers that don’t appear in checkpoints. The cost of CPR is checkpoint overhead, which is incurred when a mis-speculation occurs on an instruction for which a checkpoint was not created a priori. Here, CPR must recover to the immediately older checkpoint, squashing instructions older than the mis-speculation itself. In contrast, a ROB processor performs minimal recovery and only squashes instructions younger than the mis-speculation. CPROB is a hybrid Register management scheme that preserves CPR’s aggressive reclamation while opportunistically minimizing checkpoint overhead. CPROB extends CPR to track and hold the Registers needed to perform minimal recovery to un-executed branches within each checkpoint. Recovery Registers are held on a best-effort basis only. A checkpoint’s recovery Registers can be freed spontaneously when all branches in the checkpoint execute. They can also be aggressively victimized if dispatch needs Registers to proceed. CPROB naturally adapts the Register reclamation policy to dynamic branch behavior. When branch mis-predictions are infrequent and Registers are needed to support a large window, CPROB victimizes Registers and behaves like CPR. When mis-predictions are frequent and the window is small, CPROB holds on to Registers and behaves like ROB. As a result, it out-performs both CPR and ROB for a given program. This performance improvement, combined with reduced checkpoint overhead, makes CPROB more energy-efficient than either ROB or CPR. I
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Physical Register reference counting
IEEE Computer Architecture Letters, 2008Co-Authors: Amir RothAbstract:Several proposed techniques including CPR (checkpoint processing and recovery) and NoSQ (no store queue) rely on reference counting to manage Physical Registers. However, the Register reference counting mechanism itself has received surprisingly little attention. This paper fills this gap by describing potential Register reference counting schemes for NoSQ, CPR, and a hypothetical NoSQ/CPR hybrid. Although previously described in terms of binary counters, we find that reference counts are actually more naturally represented as matrices. Binary representations can be used as an optimization in specific situations.
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Reno: A rename-based instruction optimizer
2005Co-Authors: Vlad Petric, Tingting Sha, Amir RothAbstract:The effectiveness of static code optimizations--including static optimizations performed "just-in-time"--is limited by some basic constraints: (i) a limited number of logical Registers, (ii) a function- or region-bounded optimization scope, and (iii) the requirement that transformations be valid along all possible paths. RENO is a modified MIPS-R10000 style Register renaming mechanism augmented with Physical Register reference counting that uses map-table "short-circuiting " to implement dynamic versions of several well-known static optimizations: move elimination, common subexpression elimination, Register allocation, and constant folding. Because it implements these optimizations dynamically, RENO can overcome some of the limitations faced by static compilers and apply optimizations where static compilers cannot. RENO has many more Registers at its disposal--the entire Physical Register file. Its optimizations naturally cross function or any other compilation region boundary. And RENO performs optimizations along the dynamic path without being impacted by other, non-taken paths. If the dynamic path proves incorrect due to mispeculations, RENO optimizations are naturally rolled back along with the code they optimize. RENO unifies several previously proposed optimizations: dynamic move elimination [14] (RENOME), Register integration [24] (RENOCSE), and speculative memory bypassing (the dynamic counterpart o
Manolis Kaliorakis - One of the best experts on this subject based on the ideXlab platform.
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merlin exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment
International Symposium on Computer Architecture, 2017Co-Authors: Manolis Kaliorakis, Dimitris Gizopoulos, Ramon Canal, Antonio GonzalezAbstract:Early reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural structures modeled in performance simulators is an accurate method to measure their Architectural Vulnerability Factor (AVF) but requires excessively long campaigns to obtain high statistical significance. We propose MeRLiN1, a methodology to boost microarchitecture level injection-based reliability assessment by several orders of magnitude and keep the accuracy of the assessment unaffected even for large injection campaigns with very high statistical significance. The core of MeRLiN is the grouping of faults of an initial list in equivalent classes. All faults in the same group target equivalent vulnerable intervals of program execution ending up to the same static instruction that reads the faulty entries. Faults in the same group occur in different times and entries of a structure and it is extremely likely that they all have the same effect in program execution; thus, fault injection is performed only on a few representatives from each group. We evaluate MeRLiN for different sizes of the Physical Register file, the store queue and the first level data cache of a contemporary microarchitecture running MiBench and SPEC CPU2006 benchmarks. For all our experiments, MeRLiN is from 2 to 3 orders of magnitude faster than an extremely high statistical significant injection campaign, reporting the same reliability measurements with negligible loss of accuracy. Finally, we theoretically analyze MeRLiN's statistical behavior to further justify its accuracy.