The Experts below are selected from a list of 105 Experts worldwide ranked by ideXlab platform
Tai-hua Lu - One of the best experts on this subject based on the ideXlab platform.
-
effective hybrid test program development for software based self testing of Pipeline Processor cores
IEEE Transactions on Very Large Scale Integration Systems, 2011Co-Authors: Tai-hua Lu, Chung-ho ChenAbstract:This paper presents an effective hybrid test program for the software-based self-testing (SBST) of Pipeline Processor cores. The test program combines a deterministically developed program which explores different levels of Processor core information and a block-based random program which consists of a combination of in-order instructions, random-order instructions, return instructions, as well as instruction sequences used to trigger exception/interrupt requests. Due to the complementary nature of this hybrid test program, it can achieve Processor fault coverage that is comparable to the performance of the conventional scan chain method. The test response observation methods and their impacts on fault coverage are also investigated. We present the concept of micro observation versus macro observation and show that the most effective method of using SBST is through a multiple input signature register connected to the Processor local bus, while conventional methods that observe only the program results in the memory lead to significantly less Processor fault coverage.
-
A Hybrid Software-Based Self-Testing methodology for Embedded Processor
APPLIED COMPUTING 2008 VOLS 1-3, 2008Co-Authors: Tai-hua Lu, Chung-ho Chen, Kuen-jong LeeAbstract:Software-based self-test (SBST) is emerging as a promising technology\nfor enabling at-speed testing of high-speed embedded Processors testing\nin an SoC system. For SBST, test routine development or generation can\nbase on deterministic and random methodology. The deterministic test\nmethodology develops the test program for a Pipeline Processor using the\ninformation abstracted from its architecture model, RTL descriptions,\nand gate-level net-list for different types of Processor circuits. The\nrandom test methodology tries to make the pseudo-exhaustive testing\npossible using random instructions or patterns. The proposed methodology\nimproves coverage for structural faults using both deterministic and\nrandom development of the test code. Not only can the deterministic test\nprogram test lots of faults using very small code size, but also the\nrandom test program can help detect some of the faults that the\ndeterministic test program is difficult to test. We demonstrated the\nfeasibility of the proposed methodology by the achieved fault coverage,\ntest program size, and testing cycle count on a complex Pipeline\nProcessor core. Comparisons with previous work are also made.\nExperimental results show its potential as an effective method for\npractical use.
Kirat Pal Singh - One of the best experts on this subject based on the ideXlab platform.
-
performance improvement in mips Pipeline Processor based on fpga
International journal of engineering and technology, 2016Co-Authors: Kirat Pal SinghAbstract:The paper describes the design and synthesis of a basic 5 stage Pipelined MIPS-32 Processor for finding the longer path delay using different process technologies. The large propagation delay or critical path within the circuit and improving the hardware which causes delay is a standard method for increasing the performance. The organization of Pipeline stages in such a way that Pipeline can be clocked at a high frequency. The design has been synthesized at different process technologies targeting using Spartan3, Spartan6, Virtex4, Virtex5 and Virtex6 devices. The synthesis report indicates that critical path delay is located in execution unit. The maximum critical path delay is 41.405ns at 90nm technology and minimum critical path delay is 6.57ns at 40nm technology. The performance comparison result at different technologies shows that Pipeline Processor can work at 178MHz in 40nm technology i.e. 49.7% better than other technologies.
-
vhdl implementation of a mips 32 Pipeline Processor
International journal of applied engineering research, 2012Co-Authors: Kirat Pal Singh, Shivani ParmarAbstract:This paper presents the design and implement a basic five stage Pipelined MIPS-32 CPU. Particular attention will be paid to the reduction of clock cycles for lower instruction latency as well as taking advantage of high-speed components in an attempt to reach a clock speed of at least 100 MHz. The final results allowed the CPU to be run at over 200 MHz with a very reasonable chip area of around 900,000 nm2.
-
Design of High Performance MIPS-32 Pipeline Processor
2012Co-Authors: Dilip Kumar, Kirat Pal SinghAbstract:The paper describes the design and synthesis of a basic 5 stage Pipelined MIPS-32 Processor for finding the longer path delay using different process technologies. The large propagation delay or critical path within the circuit and improving the hardware which causes delay is a standard method for increasing the performance. The organization of Pipeline stages in such a way that Pipeline can be clocked at a high frequency. The design has been synthesized at different process technologies targeting using Spartan3, Spartan6, Virtex4, Virtex5 and Virtex6 devices. The synthesis report indicates that critical path delay is located in execution unit. The maximum critical path delay is 41.405ns at 90nm technology and minimum critical path delay is 6.57ns at 40nm technology. The performance comparison result at different technologies shows that Pipeline Processor can work at 178MHz in 40nm technology i.e. 49.7% better than other technologies. KeywordsMIPS Processor, Datapath, ALU, register file, Pipeline
Kuen-jong Lee - One of the best experts on this subject based on the ideXlab platform.
-
A Hybrid Software-Based Self-Testing methodology for Embedded Processor
APPLIED COMPUTING 2008 VOLS 1-3, 2008Co-Authors: Tai-hua Lu, Chung-ho Chen, Kuen-jong LeeAbstract:Software-based self-test (SBST) is emerging as a promising technology\nfor enabling at-speed testing of high-speed embedded Processors testing\nin an SoC system. For SBST, test routine development or generation can\nbase on deterministic and random methodology. The deterministic test\nmethodology develops the test program for a Pipeline Processor using the\ninformation abstracted from its architecture model, RTL descriptions,\nand gate-level net-list for different types of Processor circuits. The\nrandom test methodology tries to make the pseudo-exhaustive testing\npossible using random instructions or patterns. The proposed methodology\nimproves coverage for structural faults using both deterministic and\nrandom development of the test code. Not only can the deterministic test\nprogram test lots of faults using very small code size, but also the\nrandom test program can help detect some of the faults that the\ndeterministic test program is difficult to test. We demonstrated the\nfeasibility of the proposed methodology by the achieved fault coverage,\ntest program size, and testing cycle count on a complex Pipeline\nProcessor core. Comparisons with previous work are also made.\nExperimental results show its potential as an effective method for\npractical use.
Chung-ho Chen - One of the best experts on this subject based on the ideXlab platform.
-
effective hybrid test program development for software based self testing of Pipeline Processor cores
IEEE Transactions on Very Large Scale Integration Systems, 2011Co-Authors: Tai-hua Lu, Chung-ho ChenAbstract:This paper presents an effective hybrid test program for the software-based self-testing (SBST) of Pipeline Processor cores. The test program combines a deterministically developed program which explores different levels of Processor core information and a block-based random program which consists of a combination of in-order instructions, random-order instructions, return instructions, as well as instruction sequences used to trigger exception/interrupt requests. Due to the complementary nature of this hybrid test program, it can achieve Processor fault coverage that is comparable to the performance of the conventional scan chain method. The test response observation methods and their impacts on fault coverage are also investigated. We present the concept of micro observation versus macro observation and show that the most effective method of using SBST is through a multiple input signature register connected to the Processor local bus, while conventional methods that observe only the program results in the memory lead to significantly less Processor fault coverage.
-
A Hybrid Software-Based Self-Testing methodology for Embedded Processor
APPLIED COMPUTING 2008 VOLS 1-3, 2008Co-Authors: Tai-hua Lu, Chung-ho Chen, Kuen-jong LeeAbstract:Software-based self-test (SBST) is emerging as a promising technology\nfor enabling at-speed testing of high-speed embedded Processors testing\nin an SoC system. For SBST, test routine development or generation can\nbase on deterministic and random methodology. The deterministic test\nmethodology develops the test program for a Pipeline Processor using the\ninformation abstracted from its architecture model, RTL descriptions,\nand gate-level net-list for different types of Processor circuits. The\nrandom test methodology tries to make the pseudo-exhaustive testing\npossible using random instructions or patterns. The proposed methodology\nimproves coverage for structural faults using both deterministic and\nrandom development of the test code. Not only can the deterministic test\nprogram test lots of faults using very small code size, but also the\nrandom test program can help detect some of the faults that the\ndeterministic test program is difficult to test. We demonstrated the\nfeasibility of the proposed methodology by the achieved fault coverage,\ntest program size, and testing cycle count on a complex Pipeline\nProcessor core. Comparisons with previous work are also made.\nExperimental results show its potential as an effective method for\npractical use.
Masaharu Imai - One of the best experts on this subject based on the ideXlab platform.
-
a Processor generation method from instruction behavior description based on specification of Pipeline stages and functional units
Asia and South Pacific Design Automation Conference, 2007Co-Authors: T Shiro, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu ImaiAbstract:This paper proposes a method for generating a Pipeline Processor from the behavior description of instructions. In the proposed method, a micro-operation description is generated by complementing the behavior description with specifications of the Pipeline stages, such as the number of Pipeline stages, the attributes of each stage. From the behavior description, software development tools, such as an instruction-set simulator (ISS), a compiler, and an assembler can be generated, and a synthesizable HDL description of a Processor can be generated from the micro-operation description. Compared with the conventional method of writing individual descriptions, the proposed method can dramatically reduce the code size of the architectural description language and the design time without degrading the design quality. As a result, a design space exploration can be performed efficiently.
-
CHARME - Verification challenges in configurable Processor design with ASIP meister
Lecture Notes in Computer Science, 2005Co-Authors: Masaharu Imai, Akira KitajimaAbstract:In this presentation, several verification problems in configurable Processor design synthesis are illustrated. Our research group (PEAS Project) has been developing a novel design methodology of configurable Processor, that includes higher level Processor specification description, HDL description generation from the specification, Flexible Hardware Model (FHM) for resource management for HDL generation, compiler and ISS (Instruction Set level Simulator) generation. Based on this methodology, we develop a configurable Processor design environment named ASIP Meister. The Processor design flow using ASIP Meister is as follows: Firstly, a designer describes an instruction set architecture as a specification of a target Processor including Pipeline specification, instruction formats, behavior description of each instruction and interrupts, data type specification, and so on. Secondly, the designer select resources for modules to implement some functions of instructions from FHM database, that can generate various resources, such as registers, selectors, adders, shifters, etc. Thirdly, the designer describes micro-operation level behavior description with selected resources in each Pipeline stages for each instruction and interrupt. Finally, HDL description of the Pipeline Processor and machine-depend compiler information for a retargetable compiler are generated. One of the most important issues in such a generation based design methodology is how to keep the consistency between a given instruction set architecture specification and implementations. In the most state-of-the-art Processor core generation systems, including ASIP Meister, however, there are no efficient formal methods to guarantee the correctness of a generated HDL description and compiler that implement the given specification of instruction set architecture. We will explain several problems that are expected to be solved by applying formal verification techniques as reasonable solutions.