The Experts below are selected from a list of 228 Experts worldwide ranked by ideXlab platform
Chihkong Ken Yang - One of the best experts on this subject based on the ideXlab platform.
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a 6 gsamples s multi level decision feedback equalizer embedded in a 4 bit time interleaved Pipeline a d converter
IEEE Journal of Solid-state Circuits, 2006Co-Authors: A Varzaghani, Chihkong Ken YangAbstract:A 4-bit 6-GS/s Pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-/spl mu/m CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each Pipeline Stage; hence the effective feedback delay requirement is relaxed by 6/spl times/. Code-overlapping of the 1.5-bit Pipeline Stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with /spl plusmn/0.25 LSB and /spl plusmn/0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8/spl times/1.6 mm/sup 2/ chip consumes 780 mW of power from a 1.8-V power supply.
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a 6 gsamples s multi level decision feedback equalizer embedded in a 4 bit time interleaved Pipeline a d converter
Symposium on VLSI Circuits, 2006Co-Authors: A Varzaghani, Chihkong Ken YangAbstract:A 4-bit 6-GS/s Pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-μm CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each Pipeline Stage; hence the effective feedback delay requirement is relaxed by 6x. Code-overlapping of the 1.5-bit Pipeline Stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with ±0.25 LSB and ±0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8 x 1.6 mm 2 chip consumes 780 mW of power from a 1.8-V power supply.
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a 600ms s 5 bit Pipelined analog to digital converter for serial link applications
Symposium on VLSI Circuits, 2004Co-Authors: A Varzaghani, Chihkong Ken YangAbstract:Design of a high-speed low-to-medium resolution analog-to-digital converter with closed-loop Pipeline structure has been investigated. We demonstrate a single-path 600MS/s, 5-bit ADC. It is optimally designed to meet the requirements of a serial-link receiver. For high input-bandwidth, total input-capacitance is only 170fF. At high frequencies, to improve resolution beyond the amplifier-settling limit, the reference voltage of each Pipeline-Stage is digitally tuned. The chip is fabricated in 0.18 /spl mu/m CMOS technology and consumes 70mW at 1.8V power-supply.
A Varzaghani - One of the best experts on this subject based on the ideXlab platform.
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a 6 gsamples s multi level decision feedback equalizer embedded in a 4 bit time interleaved Pipeline a d converter
IEEE Journal of Solid-state Circuits, 2006Co-Authors: A Varzaghani, Chihkong Ken YangAbstract:A 4-bit 6-GS/s Pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-/spl mu/m CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each Pipeline Stage; hence the effective feedback delay requirement is relaxed by 6/spl times/. Code-overlapping of the 1.5-bit Pipeline Stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with /spl plusmn/0.25 LSB and /spl plusmn/0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8/spl times/1.6 mm/sup 2/ chip consumes 780 mW of power from a 1.8-V power supply.
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a 6 gsamples s multi level decision feedback equalizer embedded in a 4 bit time interleaved Pipeline a d converter
Symposium on VLSI Circuits, 2006Co-Authors: A Varzaghani, Chihkong Ken YangAbstract:A 4-bit 6-GS/s Pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-μm CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each Pipeline Stage; hence the effective feedback delay requirement is relaxed by 6x. Code-overlapping of the 1.5-bit Pipeline Stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with ±0.25 LSB and ±0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8 x 1.6 mm 2 chip consumes 780 mW of power from a 1.8-V power supply.
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a 600ms s 5 bit Pipelined analog to digital converter for serial link applications
Symposium on VLSI Circuits, 2004Co-Authors: A Varzaghani, Chihkong Ken YangAbstract:Design of a high-speed low-to-medium resolution analog-to-digital converter with closed-loop Pipeline structure has been investigated. We demonstrate a single-path 600MS/s, 5-bit ADC. It is optimally designed to meet the requirements of a serial-link receiver. For high input-bandwidth, total input-capacitance is only 170fF. At high frequencies, to improve resolution beyond the amplifier-settling limit, the reference voltage of each Pipeline-Stage is digitally tuned. The chip is fabricated in 0.18 /spl mu/m CMOS technology and consumes 70mW at 1.8V power-supply.
D A Johns - One of the best experts on this subject based on the ideXlab platform.
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an 11 bit 45 ms s Pipelined adc with rapid calibration of dac errors in a multibit Pipeline Stage
IEEE Journal of Solid-state Circuits, 2008Co-Authors: I Ahmed, D A JohnsAbstract:A technique to rapidly correct for both DAC and gain errors in the multibit first Stage of an 11-bit Pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 104 clock cycles.
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an 11 bit 45ms s Pipelined adc with rapid calibration of dac errors in a multi bit Pipeline Stage
European Solid-State Circuits Conference, 2007Co-Authors: I Ahmed, D A JohnsAbstract:A technique to rapidly correct for DAC errors in the multi-bit first Stage of an 11-bit Pipelined ADC is presented. Using a split-ADC approach the digital background scheme is validated with a proof-of-concept prototype fabricated in 1.8 V 0.18 mum CMOS, where the calibration scheme improves the INL of the ADC at fs=45 MS/s, from +6.1/-6.4 LSB to +1.1/-1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in ~104 clock cycles.
S. Singh - One of the best experts on this subject based on the ideXlab platform.
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A tree based router search engine architecture with single port memories
32nd International Symposium on Computer Architecture (ISCA'05), 2005Co-Authors: F. Baboescu, D.m. Tullsen, G. Rosu, S. SinghAbstract:Pipelined forwarding engines are used in core router to meet speed demands. Tree-based searches are Pipelined across a number of Stages to achieve high throughput, but this results in unevenly distributed memory. To address this imbalance, conventional approaches use either complex dynamic memory allocation schemes or over-provision each of the Pipeline Stages. This paper describes the microarchitecture of a novel network search processor which provides both high execution throughput and balanced memory distributor by dividing the tree into subtrees and allocating each subtree separately, allowing searches to begin at any Pipeline Stage. The architecture is validated by implementing and simulating state of the art solutions for IPv4 lookup, VPN forwarding and packet classification. The new Pipeline scheme and memory allocator can provide searches with a memory allocation, efficiency that is within 1% of non-Pipelined schemes.
I Ahmed - One of the best experts on this subject based on the ideXlab platform.
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an 11 bit 45 ms s Pipelined adc with rapid calibration of dac errors in a multibit Pipeline Stage
IEEE Journal of Solid-state Circuits, 2008Co-Authors: I Ahmed, D A JohnsAbstract:A technique to rapidly correct for both DAC and gain errors in the multibit first Stage of an 11-bit Pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 104 clock cycles.
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an 11 bit 45ms s Pipelined adc with rapid calibration of dac errors in a multi bit Pipeline Stage
European Solid-State Circuits Conference, 2007Co-Authors: I Ahmed, D A JohnsAbstract:A technique to rapidly correct for DAC errors in the multi-bit first Stage of an 11-bit Pipelined ADC is presented. Using a split-ADC approach the digital background scheme is validated with a proof-of-concept prototype fabricated in 1.8 V 0.18 mum CMOS, where the calibration scheme improves the INL of the ADC at fs=45 MS/s, from +6.1/-6.4 LSB to +1.1/-1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in ~104 clock cycles.