The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform

Jan Reineke - One of the best experts on this subject based on the ideXlab platform.

  • Design and analysis of SIC: a provably timing-predictable Pipelined Processor core
    Real-Time Systems, 2019
    Co-Authors: Sebastian Hahn, Jan Reineke
    Abstract:

    We introduce the strictly in-order core (SIC), a timing-predictable Pipelined Processor core. SIC is provably timing compositional and free of timing anomalies. This enables precise and efficient worst-case execution time (WCET) and multi-core timing analysis. SIC’s key underlying property is the monotonicity of its transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully eliminating some of the dependencies between consecutive instructions from a standard in-order pipeline design. We present a formal proof framework based on satisfiability modulo theories that is able to automatically verify SIC’s timing predictability. SIC preserves most of the benefits of pipelining: it is only about 6–7% slower than a conventional non-strict in-order Pipelined Processor. Its timing predictability enables orders-of-magnitude faster WCET and multi-core timing analysis than conventional designs.

  • RTSS - Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core
    Real-Time Systems, 2018
    Co-Authors: Sebastian Hahn, Jan Reineke
    Abstract:

    We introduce the strictly in-order core (SIC), a timing-predictable Pipelined Processor core. SIC is provably timing compositional and free of timing anomalies. This enables precise and efficient worst-case execution time (WCET) and multi-core timing analysis. SIC's key underlying property is the monotonicity of its transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully eliminating some of the dependencies between consecutive instructions from a standard in-order pipeline design. SIC preserves most of the benefits of pipelining: it is only about 6-7% slower than a conventional Pipelined Processor. Its timing predictability enables orders-of-magnitude faster WCET and multi-core timing analysis than conventional designs.

  • Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core
    2018 IEEE Real-Time Systems Symposium (RTSS), 2018
    Co-Authors: Sebastian Hahn, Jan Reineke
    Abstract:

    We introduce the strictly in-order core (SIC), a timing-predictable Pipelined Processor core. SIC is provably timing compositional and free of timing anomalies. This enables precise and efficient worst-case execution time (WCET) and multi-core timing analysis. SIC's key underlying property is the monotonicity of its transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully eliminating some of the dependencies between consecutive instructions from a standard in-order pipeline design. SIC preserves most of the benefits of pipelining: it is only about 6-7% slower than a conventional Pipelined Processor. Its timing predictability enables orders-of-magnitude faster WCET and multi-core timing analysis than conventional designs.

T. Enomoto - One of the best experts on this subject based on the ideXlab platform.

  • Design for testability in a 200 MFLOPS vector-Pipelined Processor (VPP)-ULSI
    Proceedings First Asian Test Symposium (ATS `92), 1992
    Co-Authors: Y. Hagihara, C. Ohkubo, F. Okamoto, H. Yamada, M. Takada, T. Enomoto
    Abstract:

    The authors describe design for testability (DFT) techniques implemented in a 200 MFLOPS 64-bit floating point vector-Pipelined Processor (VPP) ULSI. Scan tests were implemented into the central control unit (CCU), as well as into the input/output buffers, which are served by a boundary scan (BS) chain. Newly developed random pattern built-in self tests (BISTs) were implemented into the register file (RF), as well as into two arithmetic units (ADD/SFT and MPY/DIV/LU). Fault coverage for the RF (2-port SRAMs) was 100%. Average fault coverage for Pipelined arithmetic units, achieved by a BIST with approximately 1,000,000(2/sup 20/) random patterns, was 98%. Combination of scan test and BIST-internal partial scan-achieves a partial-scan test of the arithmetic units and 99.6% fault coverage for the MPY/DIV/LU.

  • A 200-MFLOPS 100-MHz 64-b BiCMOS vector-Pipelined Processor (VPP) ULSI
    IEEE Journal of Solid-State Circuits, 1991
    Co-Authors: F. Okamoto, Y. Hagihara, C. Ohkubo, H. Yamada, N. Nishi, T. Enomoto
    Abstract:

    The first single-chip 64-b vector-Pipelined Processor (VPP) ULSI is described. It executes vector operations indispensable to high-speed scientific computation. The VPP ULSI attains a 200-MFLOPS peak performance at a 100-MHz clock frequency. This extremely high performance is made possible by the integration on the VPP of a 64-b five-stage Pipelined adder/shifter, a 64-b five-stage Pipelined multiplier/divider/logic operation unit, and a 40-kb register file. Various new high-speed circuit techniques have been also developed for 100-MHz operations. The chip, which was fabricated with a 0.8- mu m BiCMOS and triple-layer metallization process technology, has a 17.2-mm*17.3-mm area and contains about 693 K transistors. It consumes 13.2 W at a 100-MHz clock frequency with a single 5-V power supply.

Sebastian Hahn - One of the best experts on this subject based on the ideXlab platform.

  • Design and analysis of SIC: a provably timing-predictable Pipelined Processor core
    Real-Time Systems, 2019
    Co-Authors: Sebastian Hahn, Jan Reineke
    Abstract:

    We introduce the strictly in-order core (SIC), a timing-predictable Pipelined Processor core. SIC is provably timing compositional and free of timing anomalies. This enables precise and efficient worst-case execution time (WCET) and multi-core timing analysis. SIC’s key underlying property is the monotonicity of its transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully eliminating some of the dependencies between consecutive instructions from a standard in-order pipeline design. We present a formal proof framework based on satisfiability modulo theories that is able to automatically verify SIC’s timing predictability. SIC preserves most of the benefits of pipelining: it is only about 6–7% slower than a conventional non-strict in-order Pipelined Processor. Its timing predictability enables orders-of-magnitude faster WCET and multi-core timing analysis than conventional designs.

  • RTSS - Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core
    Real-Time Systems, 2018
    Co-Authors: Sebastian Hahn, Jan Reineke
    Abstract:

    We introduce the strictly in-order core (SIC), a timing-predictable Pipelined Processor core. SIC is provably timing compositional and free of timing anomalies. This enables precise and efficient worst-case execution time (WCET) and multi-core timing analysis. SIC's key underlying property is the monotonicity of its transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully eliminating some of the dependencies between consecutive instructions from a standard in-order pipeline design. SIC preserves most of the benefits of pipelining: it is only about 6-7% slower than a conventional Pipelined Processor. Its timing predictability enables orders-of-magnitude faster WCET and multi-core timing analysis than conventional designs.

  • Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core
    2018 IEEE Real-Time Systems Symposium (RTSS), 2018
    Co-Authors: Sebastian Hahn, Jan Reineke
    Abstract:

    We introduce the strictly in-order core (SIC), a timing-predictable Pipelined Processor core. SIC is provably timing compositional and free of timing anomalies. This enables precise and efficient worst-case execution time (WCET) and multi-core timing analysis. SIC's key underlying property is the monotonicity of its transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully eliminating some of the dependencies between consecutive instructions from a standard in-order pipeline design. SIC preserves most of the benefits of pipelining: it is only about 6-7% slower than a conventional Pipelined Processor. Its timing predictability enables orders-of-magnitude faster WCET and multi-core timing analysis than conventional designs.

F. Okamoto - One of the best experts on this subject based on the ideXlab platform.

  • Floating-point datapaths with online built-in self speed test
    IEEE Journal of Solid-State Circuits, 1997
    Co-Authors: Y. Hagihara, F. Okamoto, S. Inui, M. Nishida, T. Nakamura, H. Yamada
    Abstract:

    This paper describes floating-point (FP) datapaths developed for graphics and simulation applications. The datapaths are fabricated using 0.35 /spl mu/m CMOS technology and embedded in a 125 MHz, 291 MFLOPS vector Pipelined Processor for use in supercomputers. A new online test technique has been developed for the purpose of improving reliability under actual operating conditions. The technique makes it easy to detect not only static faults but also delay faults, which has traditionally been difficult.

  • Floating point datapaths with on-line built-in self speed test
    Proceedings of Custom Integrated Circuits Conference, 1996
    Co-Authors: Y. Hagihara, F. Okamoto, S. Inui, M. Nishida, T. Nakamura, H. Yamada
    Abstract:

    This paper describes floating point (FP) datapaths developed for graphics and simulation applications. The datapaths are fabricated using 0.35 /spl mu/m CMOS technology and embedded in a 125 MHz, 290 MFLOPS vector Pipelined Processor for use in supercomputers. A new on-line test technique has been developed for the purpose of improving reliability under actual operating conditions. The technique makes it easy to detect not only static faults but also delay faults, which have traditionally been difficult to detect.

  • Design for testability in a 200 MFLOPS vector-Pipelined Processor (VPP)-ULSI
    Proceedings First Asian Test Symposium (ATS `92), 1992
    Co-Authors: Y. Hagihara, C. Ohkubo, F. Okamoto, H. Yamada, M. Takada, T. Enomoto
    Abstract:

    The authors describe design for testability (DFT) techniques implemented in a 200 MFLOPS 64-bit floating point vector-Pipelined Processor (VPP) ULSI. Scan tests were implemented into the central control unit (CCU), as well as into the input/output buffers, which are served by a boundary scan (BS) chain. Newly developed random pattern built-in self tests (BISTs) were implemented into the register file (RF), as well as into two arithmetic units (ADD/SFT and MPY/DIV/LU). Fault coverage for the RF (2-port SRAMs) was 100%. Average fault coverage for Pipelined arithmetic units, achieved by a BIST with approximately 1,000,000(2/sup 20/) random patterns, was 98%. Combination of scan test and BIST-internal partial scan-achieves a partial-scan test of the arithmetic units and 99.6% fault coverage for the MPY/DIV/LU.

  • A 200-MFLOPS 100-MHz 64-b BiCMOS vector-Pipelined Processor (VPP) ULSI
    IEEE Journal of Solid-State Circuits, 1991
    Co-Authors: F. Okamoto, Y. Hagihara, C. Ohkubo, H. Yamada, N. Nishi, T. Enomoto
    Abstract:

    The first single-chip 64-b vector-Pipelined Processor (VPP) ULSI is described. It executes vector operations indispensable to high-speed scientific computation. The VPP ULSI attains a 200-MFLOPS peak performance at a 100-MHz clock frequency. This extremely high performance is made possible by the integration on the VPP of a 64-b five-stage Pipelined adder/shifter, a 64-b five-stage Pipelined multiplier/divider/logic operation unit, and a 40-kb register file. Various new high-speed circuit techniques have been also developed for 100-MHz operations. The chip, which was fabricated with a 0.8- mu m BiCMOS and triple-layer metallization process technology, has a 17.2-mm*17.3-mm area and contains about 693 K transistors. It consumes 13.2 W at a 100-MHz clock frequency with a single 5-V power supply.

Y. Hagihara - One of the best experts on this subject based on the ideXlab platform.

  • Floating-point datapaths with online built-in self speed test
    IEEE Journal of Solid-State Circuits, 1997
    Co-Authors: Y. Hagihara, F. Okamoto, S. Inui, M. Nishida, T. Nakamura, H. Yamada
    Abstract:

    This paper describes floating-point (FP) datapaths developed for graphics and simulation applications. The datapaths are fabricated using 0.35 /spl mu/m CMOS technology and embedded in a 125 MHz, 291 MFLOPS vector Pipelined Processor for use in supercomputers. A new online test technique has been developed for the purpose of improving reliability under actual operating conditions. The technique makes it easy to detect not only static faults but also delay faults, which has traditionally been difficult.

  • Floating point datapaths with on-line built-in self speed test
    Proceedings of Custom Integrated Circuits Conference, 1996
    Co-Authors: Y. Hagihara, F. Okamoto, S. Inui, M. Nishida, T. Nakamura, H. Yamada
    Abstract:

    This paper describes floating point (FP) datapaths developed for graphics and simulation applications. The datapaths are fabricated using 0.35 /spl mu/m CMOS technology and embedded in a 125 MHz, 290 MFLOPS vector Pipelined Processor for use in supercomputers. A new on-line test technique has been developed for the purpose of improving reliability under actual operating conditions. The technique makes it easy to detect not only static faults but also delay faults, which have traditionally been difficult to detect.

  • Design for testability in a 200 MFLOPS vector-Pipelined Processor (VPP)-ULSI
    Proceedings First Asian Test Symposium (ATS `92), 1992
    Co-Authors: Y. Hagihara, C. Ohkubo, F. Okamoto, H. Yamada, M. Takada, T. Enomoto
    Abstract:

    The authors describe design for testability (DFT) techniques implemented in a 200 MFLOPS 64-bit floating point vector-Pipelined Processor (VPP) ULSI. Scan tests were implemented into the central control unit (CCU), as well as into the input/output buffers, which are served by a boundary scan (BS) chain. Newly developed random pattern built-in self tests (BISTs) were implemented into the register file (RF), as well as into two arithmetic units (ADD/SFT and MPY/DIV/LU). Fault coverage for the RF (2-port SRAMs) was 100%. Average fault coverage for Pipelined arithmetic units, achieved by a BIST with approximately 1,000,000(2/sup 20/) random patterns, was 98%. Combination of scan test and BIST-internal partial scan-achieves a partial-scan test of the arithmetic units and 99.6% fault coverage for the MPY/DIV/LU.

  • A 200-MFLOPS 100-MHz 64-b BiCMOS vector-Pipelined Processor (VPP) ULSI
    IEEE Journal of Solid-State Circuits, 1991
    Co-Authors: F. Okamoto, Y. Hagihara, C. Ohkubo, H. Yamada, N. Nishi, T. Enomoto
    Abstract:

    The first single-chip 64-b vector-Pipelined Processor (VPP) ULSI is described. It executes vector operations indispensable to high-speed scientific computation. The VPP ULSI attains a 200-MFLOPS peak performance at a 100-MHz clock frequency. This extremely high performance is made possible by the integration on the VPP of a 64-b five-stage Pipelined adder/shifter, a 64-b five-stage Pipelined multiplier/divider/logic operation unit, and a 40-kb register file. Various new high-speed circuit techniques have been also developed for 100-MHz operations. The chip, which was fabricated with a 0.8- mu m BiCMOS and triple-layer metallization process technology, has a 17.2-mm*17.3-mm area and contains about 693 K transistors. It consumes 13.2 W at a 100-MHz clock frequency with a single 5-V power supply.