The Experts below are selected from a list of 306 Experts worldwide ranked by ideXlab platform
Laurent Pichon - One of the best experts on this subject based on the ideXlab platform.
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Silicon nanowires based resistors as gas sensors
Sensors and Actuators B: Chemical, 2011Co-Authors: Fouad Demami, Régis Rogel, Anne-claire Salaün, Laurent PichonAbstract:Silicon nanowires (SiNWs) are synthesized following two methods: i) the VLS (Vapor-Liquid-Solid) growth technique (bottom up approach), and ii) the sidewall spacer fabrication (top down approach) commonly used in microelectronic industry. The VLS growth technique uses gold nanoparticles to activate the vapor deposition of the precursor gas and to initiate 100 nm diameter SiNWs network growth. In the case of the sidewall spacer method, a Polysilicon Layer is deposited by LPCVD (Low Pressure Chemical Vapor Deposition) technique on SiO2 wall patterned by conventional UV lithography technique. Polysilicon film is then plasma etched. Accurate control of the etching rate leads to the formation of spacers with a 100 nm curvature radius that can be used as Polysilicon NWs. Each kind of nanowires is integrated into resistors fabrication. Electrical measurements show the potential use of these SiNWs based resistors as gas sensors for ammonia (NH3) and smoke detection.
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Electrical properties of Polysilicon nanowires for devices applications
physica status solidi (c), 2011Co-Authors: Fouad Demami, Régis Rogel, Anne-claire Salaün, Laurent PichonAbstract:Polysilicon nanowires are synthesized using the well known and low cost technique commonly used in microelectronic industry: the sidewall spacer formation technique. Polysilicon Layer is de-posited by Low Pressure Chemical Vapour Deposition technique on SiO2 wall patterned by conventional UV lithography tech-nique. Polysilicon film is then plasma etched. Accurate control of the etching rate leads to the formation of nanometric size side-wall spacers with a curvature radius as low as 100nm used as Polysilicon nanowires. These Polysilicon nanowires are first in-tegrated into the fabrication of electrical devices as resistors and electrical properties are studied in function of in situ phosphorus doping levels. I(T) measurements show that Polysilicon nanowires dark conductivity is thermally activated according to the Seto's theory. In addition, field effect transistors made with such Polysilicon nanowires used as channel region highlight promising field effect behaviour.
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silicon nanowires synthesis using top down and bottom up approaches : applications to chemical sensors
2011Co-Authors: Laurent PichonAbstract:Two types of SiNWs are synthesized, without requiring costly lithographic tools, following the VLS growth technique (bottom up approach), and the sidewall spacer realization (top down approach). Au-catalyst VLS SiNWs were synthesized and integrated into resistors and field effect transistors. In this way, a heavily phosphorous in-situ doped Polysilicon Layer was first deposited by LPCVD (Low Pressure Chemical Vapor Deposition) on a substrate capped with a SiO2 buffer Layer. This film was patterned by Reactive Ion Etching (RIE) to define the geometry of the comb shape electrodes (interdigitated structure). Au thin film ( 5 nm) was then deposited by thermal evaporation and locally removed using a lift off technique in order to define precise location for SiNWs growth. High density Au-catalyst non intentionally doped VLS-SiNWs network was then synthesized by LPCVD technique at 480°C and 40 Pa using silane (SiH4) as precursor gas. Due to the length of the SiNWs, which can exceed 20 µm, bridges and contacts between SiNWs ensure the connection of these two heavily doped Polysilicon islands leading to the formation of devices in a 3D configuration. This synthesis results in a tangled growth of 100 nm diameter SiNWs insuring electrical contact between the two doped electrodes. The sidewall spacer method is an alternative way to synthesize SiNWs in a 2D configuration. At first, a dielectric film is deposited and patterned into islands by conventional UV lithography. Then, an undoped amorphous silicon Layer is deposited by LPCVD at 550°C and 90 Pa, and crystallized by thermal annealing under vacuum at 600°C during 12 hours. Accurate control of this Polysilicon Layer RIE rate leads to the formation of nanometric size sidewall spacers that can be used as nanowires. Polysilicon NWs with a 100 nm or 50 nm curvature radius are the synthesized and integrated into coplanar structure (resistors, TFT). These two types of SiNWs based devices are integrated into low temperature (
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Silicon nanowires synthesis for chemical sensor applications
2010Co-Authors: Fouad Demami, Régis Rogel, Anne-claire Salaün, Laurent PichonAbstract:Silicon nanowires (SiNWs) are synthesized following two methods: i) the VLS (Vapor-Liquid-Solid) growth technique (bottom up approach), and ii) the sidewall spacer fabrication (top down approach) commonly used in microelectronic industry. The VLS growth technique uses gold nanoparticles to activate the vapor deposition of the precursor gas and initiate a 100 nm diameter SiNWs network growth. In the case of the sidewall spacer method, a Polysilicon Layer is deposited by LPCVD (Low Pressure Chemical Vapor Deposition) technique on SiO2 wall patterned by conventional UV lithography technique. Polysilicon film is then plasma etched. Accurate control of the etching rate leads to the formation of spacers with a 100 nm curvature radius that can be used as Polysilicon NWs. Each kind of nanowires is integrated into resistors fabrication. Electrical measurements show the potential usefulness of these SiNWs as chemical sensors.
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Fabrication of polycrystalline silicon nanowires using conventional UV lithography
2009Co-Authors: Fouad Demami, Régis Rogel, Laurent Pichon, Anne-claire SalaünAbstract:Silicon nanowires are processed by using the sidewall spacer formation technique. This technique uses craftily a drawback of anisotropic etching to go beyond optical limits with conventional UV lithography for precision patterns. The final width of the spacer is controlled by the steepness of the etching side and by the uniformity of the wall recovering Layer. In our process, a Polysilicon Layer is deposited by low pressure chemical vapour deposition technique on SiO2 wall network patterned by conventional UV lithography technique. Accurate control of the etching rate of the Polysilicon leads to the formation of nanometric size sidewall spacers with a curvature radius below 100nm. Networks of such parallel Polysilicon nanowires were electrically tested in function of temperature (530K300K) with thermal activation EA ~ 0.3 eV
Olivier Bonnaud - One of the best experts on this subject based on the ideXlab platform.
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Thin film transistors fabricated by in situ doped unhydrogenated Polysilicon films obtained by solid phase crystallization
Semiconductor Science and Technology, 2001Co-Authors: Laurent Pichon, K. Mourgues, F. Raoult, Tayeb Mohammed-brahim, K. Kis-sion, D. Briand, Olivier BonnaudAbstract:High-mobility low-temperature (≤600 °C) unhydrogenated in situ doped Polysilicon thin film transistors (TFTs) are made. Polysilicon Layers are grown by a low pressure chemical vapour deposition (LPCVD) technique and crystallized in a vacuum by thermal annealing. The source and drain regions are in situ doped. The gate insulator is made of an atmospheric pressure chemical vapour deposition (APCVD) silicon dioxide. Hydrogen passivation is not performed on the transistors. One type of transistor is made of two Polysilicon Layers, the other one is fabricated from a single Polysilicon Layer. The electrical properties are better for transistors made of a single Polysilicon Layer: a low threshold voltage (1.2 V), a subthreshold slope S = 0.7 V/dec, a high field effect mobility (≈100 cm2 V-1 s-1) and an on/off-state current ratio higher than 107 for a drain voltage Vds = 1 V. At low drain voltage, for both transistors, the off-state current results from a pure thermal emission of trapped carriers. However, at high drain voltage, the electrical behaviour is different: in the case of single Polysilicon TFTs, the current obeys the field-assisted (Poole-Frenkel) thermal emission model of trapped carriers while for TFTs made of two Polysilicon Layers, the higher off-state current results from a field-enhanced thermal emission.
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A Low Temperature Process (⩽600°C) of Unhydrogenated In-Situ Doped Polysilicon Thin Film Transistors for Active-Matrix Applications
ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference, 1996Co-Authors: L. Pichon, K. Mourgues, F. Raoult, Olivier Bonnaud, K. Kis-sionAbstract:Low temperature unhydrogenated in-situ doped Polysilicon thin film transistors with a SiO2 deposited gate insulator are elaborated through a four-mask aluminium process. The two Polysilicon Layers, which constitute active Layer and in-situ doped source and drain regions, are deposited at a pressure (P = 90 Pα) in the amorphous state and crystallized by a thermal annealing. This last one is performed before plasma etching of the source/drain Polysilicon Layer. An oxygen plasma + RCA-type wet cleaning are ensured to obtairn a good APCVD SiO2 gate insulator/active Layer interface quality. These thin film transistors exhibit very high electrical properties: a low threshold voltage (≈ 2 V), a high field effect mobility (≫ 60 cm2/ Vs), and a high On/Off state current ratio (⩾ 107) for a drain voltage Vds = 1 V.
K. Mourgues F. Raoult T. Mohammed-brahim K. Kis-sion - One of the best experts on this subject based on the ideXlab platform.
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Thin film transistors fabricated by in-situ doped unhydrogenated Polysilicon films obtained by solid phase crystallization
Semiconductor Science and Technology, 2001Co-Authors: Laurent Pichon, K. Mourgues F. Raoult T. Mohammed-brahim K. Kis-sionAbstract:High mobility low temperature (≤ 600°C) unhydrogenated in-situ doped Polysilicon thin film transistors are made. Polysilicon Layers are grown by a LPCVD technique and crystallized in vacuum by a thermal annealing. Source and drain regions are in-situ doped. Gate insulator is made of an APCVD silicon dioxide. Hydrogen passivation is not performed on the transistors. One type of transistors is made of two Polysilicon Layers, the other one is constituted of a single Polysilicon Layer. The electrical properties are better for transistors made of single Polysilicon Layer: a low threshold voltage (1.2 V), a subthreshold slope S = 0.7 V/dec, a high field effect mobility (≈ 100 cm2/Vs) and a On/Off state current ratio higher than 107 for a drain voltage Vds = 1 V. At low drain voltage, for both transistors, the Off state current results from a pure thermal emission of trapped carriers. However, at high drain voltage, the electrical behavior is different: in the case of single Polysilicon TFTs, the current obeys the field-assisted (Poole-Frenkel) thermal emission model of trapped carriers while for TFTs made of two Polysilicon Layers, the higher Off state current results from a field-enhanced thermal emission.
K. Kis-sion - One of the best experts on this subject based on the ideXlab platform.
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Thin film transistors fabricated by in situ doped unhydrogenated Polysilicon films obtained by solid phase crystallization
Semiconductor Science and Technology, 2001Co-Authors: Laurent Pichon, K. Mourgues, F. Raoult, Tayeb Mohammed-brahim, K. Kis-sion, D. Briand, Olivier BonnaudAbstract:High-mobility low-temperature (≤600 °C) unhydrogenated in situ doped Polysilicon thin film transistors (TFTs) are made. Polysilicon Layers are grown by a low pressure chemical vapour deposition (LPCVD) technique and crystallized in a vacuum by thermal annealing. The source and drain regions are in situ doped. The gate insulator is made of an atmospheric pressure chemical vapour deposition (APCVD) silicon dioxide. Hydrogen passivation is not performed on the transistors. One type of transistor is made of two Polysilicon Layers, the other one is fabricated from a single Polysilicon Layer. The electrical properties are better for transistors made of a single Polysilicon Layer: a low threshold voltage (1.2 V), a subthreshold slope S = 0.7 V/dec, a high field effect mobility (≈100 cm2 V-1 s-1) and an on/off-state current ratio higher than 107 for a drain voltage Vds = 1 V. At low drain voltage, for both transistors, the off-state current results from a pure thermal emission of trapped carriers. However, at high drain voltage, the electrical behaviour is different: in the case of single Polysilicon TFTs, the current obeys the field-assisted (Poole-Frenkel) thermal emission model of trapped carriers while for TFTs made of two Polysilicon Layers, the higher off-state current results from a field-enhanced thermal emission.
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A Low Temperature Process (⩽600°C) of Unhydrogenated In-Situ Doped Polysilicon Thin Film Transistors for Active-Matrix Applications
ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference, 1996Co-Authors: L. Pichon, K. Mourgues, F. Raoult, Olivier Bonnaud, K. Kis-sionAbstract:Low temperature unhydrogenated in-situ doped Polysilicon thin film transistors with a SiO2 deposited gate insulator are elaborated through a four-mask aluminium process. The two Polysilicon Layers, which constitute active Layer and in-situ doped source and drain regions, are deposited at a pressure (P = 90 Pα) in the amorphous state and crystallized by a thermal annealing. This last one is performed before plasma etching of the source/drain Polysilicon Layer. An oxygen plasma + RCA-type wet cleaning are ensured to obtairn a good APCVD SiO2 gate insulator/active Layer interface quality. These thin film transistors exhibit very high electrical properties: a low threshold voltage (≈ 2 V), a high field effect mobility (≫ 60 cm2/ Vs), and a high On/Off state current ratio (⩾ 107) for a drain voltage Vds = 1 V.
K. Mourgues - One of the best experts on this subject based on the ideXlab platform.
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Thin film transistors fabricated by in situ doped unhydrogenated Polysilicon films obtained by solid phase crystallization
Semiconductor Science and Technology, 2001Co-Authors: Laurent Pichon, K. Mourgues, F. Raoult, Tayeb Mohammed-brahim, K. Kis-sion, D. Briand, Olivier BonnaudAbstract:High-mobility low-temperature (≤600 °C) unhydrogenated in situ doped Polysilicon thin film transistors (TFTs) are made. Polysilicon Layers are grown by a low pressure chemical vapour deposition (LPCVD) technique and crystallized in a vacuum by thermal annealing. The source and drain regions are in situ doped. The gate insulator is made of an atmospheric pressure chemical vapour deposition (APCVD) silicon dioxide. Hydrogen passivation is not performed on the transistors. One type of transistor is made of two Polysilicon Layers, the other one is fabricated from a single Polysilicon Layer. The electrical properties are better for transistors made of a single Polysilicon Layer: a low threshold voltage (1.2 V), a subthreshold slope S = 0.7 V/dec, a high field effect mobility (≈100 cm2 V-1 s-1) and an on/off-state current ratio higher than 107 for a drain voltage Vds = 1 V. At low drain voltage, for both transistors, the off-state current results from a pure thermal emission of trapped carriers. However, at high drain voltage, the electrical behaviour is different: in the case of single Polysilicon TFTs, the current obeys the field-assisted (Poole-Frenkel) thermal emission model of trapped carriers while for TFTs made of two Polysilicon Layers, the higher off-state current results from a field-enhanced thermal emission.
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A Low Temperature Process (⩽600°C) of Unhydrogenated In-Situ Doped Polysilicon Thin Film Transistors for Active-Matrix Applications
ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference, 1996Co-Authors: L. Pichon, K. Mourgues, F. Raoult, Olivier Bonnaud, K. Kis-sionAbstract:Low temperature unhydrogenated in-situ doped Polysilicon thin film transistors with a SiO2 deposited gate insulator are elaborated through a four-mask aluminium process. The two Polysilicon Layers, which constitute active Layer and in-situ doped source and drain regions, are deposited at a pressure (P = 90 Pα) in the amorphous state and crystallized by a thermal annealing. This last one is performed before plasma etching of the source/drain Polysilicon Layer. An oxygen plasma + RCA-type wet cleaning are ensured to obtairn a good APCVD SiO2 gate insulator/active Layer interface quality. These thin film transistors exhibit very high electrical properties: a low threshold voltage (≈ 2 V), a high field effect mobility (≫ 60 cm2/ Vs), and a high On/Off state current ratio (⩾ 107) for a drain voltage Vds = 1 V.