The Experts below are selected from a list of 321 Experts worldwide ranked by ideXlab platform
Y. Tanabe - One of the best experts on this subject based on the ideXlab platform.
-
a current sensed high speed and low power first in first out memory using a wordline bitline swapped dual Port sram cell
IEEE Journal of Solid-state Circuits, 2002Co-Authors: Nobutaro Shibata, Mayumi Watanabe, Y. TanabeAbstract:First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO Operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-Port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words /spl times/ 8-bits FIFO memory test chip, fabricated with a 0.6-/spl mu/m CMOS process (a short effective channel length of 0.35 /spl mu/m is available for both the nMOS and pMOS), has demonstrated the 140-MHz Operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 /spl mu/W and that at 100-MHz dual-Port Operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern).
-
A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-Port SRAM cell
IEEE Journal of Solid-State Circuits, 2002Co-Authors: Nobutaro Shibata, Mayumi Watanabe, Y. TanabeAbstract:First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO Operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-Port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words /spl times/ 8-bits FIFO memory test chip, fabricated with a 0.6-/spl mu/m CMOS process (a short effective channel length of 0.35 /spl mu/m is available for both the nMOS and pMOS), has demonstrated the 140-MHz Operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 /spl mu/W and that at 100-MHz dual-Port Operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern).
Nobutaro Shibata - One of the best experts on this subject based on the ideXlab platform.
-
a current sensed high speed and low power first in first out memory using a wordline bitline swapped dual Port sram cell
IEEE Journal of Solid-state Circuits, 2002Co-Authors: Nobutaro Shibata, Mayumi Watanabe, Y. TanabeAbstract:First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO Operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-Port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words /spl times/ 8-bits FIFO memory test chip, fabricated with a 0.6-/spl mu/m CMOS process (a short effective channel length of 0.35 /spl mu/m is available for both the nMOS and pMOS), has demonstrated the 140-MHz Operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 /spl mu/W and that at 100-MHz dual-Port Operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern).
-
A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-Port SRAM cell
IEEE Journal of Solid-State Circuits, 2002Co-Authors: Nobutaro Shibata, Mayumi Watanabe, Y. TanabeAbstract:First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO Operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-Port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words /spl times/ 8-bits FIFO memory test chip, fabricated with a 0.6-/spl mu/m CMOS process (a short effective channel length of 0.35 /spl mu/m is available for both the nMOS and pMOS), has demonstrated the 140-MHz Operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 /spl mu/W and that at 100-MHz dual-Port Operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern).
Mayumi Watanabe - One of the best experts on this subject based on the ideXlab platform.
-
a current sensed high speed and low power first in first out memory using a wordline bitline swapped dual Port sram cell
IEEE Journal of Solid-state Circuits, 2002Co-Authors: Nobutaro Shibata, Mayumi Watanabe, Y. TanabeAbstract:First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO Operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-Port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words /spl times/ 8-bits FIFO memory test chip, fabricated with a 0.6-/spl mu/m CMOS process (a short effective channel length of 0.35 /spl mu/m is available for both the nMOS and pMOS), has demonstrated the 140-MHz Operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 /spl mu/W and that at 100-MHz dual-Port Operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern).
-
A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-Port SRAM cell
IEEE Journal of Solid-State Circuits, 2002Co-Authors: Nobutaro Shibata, Mayumi Watanabe, Y. TanabeAbstract:First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO Operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-Port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words /spl times/ 8-bits FIFO memory test chip, fabricated with a 0.6-/spl mu/m CMOS process (a short effective channel length of 0.35 /spl mu/m is available for both the nMOS and pMOS), has demonstrated the 140-MHz Operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 /spl mu/W and that at 100-MHz dual-Port Operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern).
Zangho Shon - One of the best experts on this subject based on the ideXlab platform.
-
estimate of ships emission in busan Port during 2009 based on activity
Journal of Environmental Sciences-china, 2011Co-Authors: Dooyeol Park, Cheolwon Hwang, Changhun Jeong, Zangho ShonAbstract:Abstract Emission of air pollutants such as nitrogen oxides (NO x ), hydrocarbons (HC), SO 2 , and particulate matter (PM) and CO 2 from ship during 2009 in Busan Port was estimated based on activity-based method. The significant fraction (> 50%) of ship emission resulted from container and general cargo ships. Emission at Port Operation mode was the most dominant compared to at sea and maneuvering modes. Emission at North Port was the largest source of air pollutants among Ports. The magnitudes of air pollutants NO x , SO 2 , HC, CO 2, and PM in Busan Port were 8.7 × 10 3 , 8.23 × 10 3 , 0.35 × 10 3 , 4.86×10 6 , and 0.67 × 10 3 ton/yr, respectively. The ratio of NO x to VOC is about 25. Our ship emission estimate is 2 times higher than that in CAPSS emission inventory. Key Words :NO x , Vessel category, Engine power, Actual speed, Emission factor 1) 1. 서 론 세계화의 가속화로 늘어가는 인적, 물적 교통량은 선박의 물동량을 증가 시키고 이로 인한 선박의 엔진배출로부터 발생하는 대기오염은 심각한 수준으로 인식되고 있다. 선박배출은 특히 선박 입 ․ 출항이 빈번한 주요 무역항 인접지역의 대기질(NO
J Ferdynus - One of the best experts on this subject based on the ideXlab platform.
-
Polish SeaPorts – Unfavorable Weather Conditions for Port Operation (Applying Methods of Complex Climatology for Data Formation to be Used by Seafaring)
TransNav: International Journal on Marine Navigation and Safety of Sea Transportation, 2012Co-Authors: J FerdynusAbstract:The use of methods of complex climatology, which treats climate as a many-year weather regime, made it possible to define the annual structure of weather states observed in seven Polish sea Ports, Elblag, Gdansk, Hel, Leba, Ustka, Kolobrzeg, and Swinoujscie. This work uses data originating from OGIMET and covers the period 2000-2009. Weather conditions that make Port Operation either difficult or even impossible are considered to be those when, during a day, negative air temperatures, cloudiness, precipitation and strong winds are observed at the same time. Once the frequency of occurrence of unfavorable weather conditions has been defined for the Port Operation then for each Port a climatogram was drawn illustrating their frequency in the following decades of a given year. Weather conditions which are unfavorable for work in Polish sea Ports are observed only in autumn and winter, and during early spring; they are most frequent in the Ports of Ustka and Gdansk. None of the described Ports exceeds 1% in their annual frequency so the conditions in Polish sea Ports may be regarded as favorable for Port Operations. The worst weather conditions are observed in the last decade of December, third decade in January, in the second and third decades in February, and in the first decade of April.
-
polish seaPorts unfavorable weather conditions for Port Operation applying methods of complex climatology for data formation to be used by seafaring
TransNav: International Journal on Marine Navigation and Safety of Sea Transportation, 2012Co-Authors: J FerdynusAbstract:The use of methods of complex climatology, which treats climate as a many-year weather regime, made it possible to define the annual structure of weather states observed in seven Polish sea Ports, Elblag, Gdansk, Hel, Leba, Ustka, Kolobrzeg, and Swinoujscie. This work uses data originating from OGIMET and covers the period 2000-2009. Weather conditions that make Port Operation either difficult or even impossible are considered to be those when, during a day, negative air temperatures, cloudiness, precipitation and strong winds are observed at the same time. Once the frequency of occurrence of unfavorable weather conditions has been defined for the Port Operation then for each Port a climatogram was drawn illustrating their frequency in the following decades of a given year. Weather conditions which are unfavorable for work in Polish sea Ports are observed only in autumn and winter, and during early spring; they are most frequent in the Ports of Ustka and Gdansk. None of the described Ports exceeds 1% in their annual frequency so the conditions in Polish sea Ports may be regarded as favorable for Port Operations. The worst weather conditions are observed in the last decade of December, third decade in January, in the second and third decades in February, and in the first decade of April.