The Experts below are selected from a list of 288 Experts worldwide ranked by ideXlab platform
B.a. Wooley - One of the best experts on this subject based on the ideXlab platform.
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a 1 3 ns 32 word spl times 32 bit three Port bicmos Register file
IEEE Journal of Solid-state Circuits, 1996Co-Authors: Chin-chieh Chao, B.a. WooleyAbstract:This paper describes a CMOS multiPort static memory cell with which it is possible to use current-switching bipolar peripheral circuits to maintain small voltage swings throughout the read access path while retaining the high density of CMOS memory arrays. An experimental 32-word/spl times/32 bit three-Port Register file has been designed and implemented using this cell. The Register file was fabricated in a 0.6-/spl mu/m BiCMOS technology and operates from a single -3.3-V power supply with ECL-compatible I/O circuits. Under nominal operating conditions at 20/spl deg/C, the measured pin-to-pin access time is 1.3 ns. The minimum write enable pulse width required is less than 1 ns, and the power dissipation, excluding the output buffers, is 650 mW at a clock rate of 100 MHz.
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A 1.3-ns 32-word/spl times/32-bit three-Port BiCMOS Register file
IEEE Journal of Solid-State Circuits, 1996Co-Authors: Chin-chieh Chao, B.a. WooleyAbstract:This paper describes a CMOS multiPort static memory cell with which it is possible to use current-switching bipolar peripheral circuits to maintain small voltage swings throughout the read access path while retaining the high density of CMOS memory arrays. An experimental 32-word/spl times/32 bit three-Port Register file has been designed and implemented using this cell. The Register file was fabricated in a 0.6-/spl mu/m BiCMOS technology and operates from a single -3.3-V power supply with ECL-compatible I/O circuits. Under nominal operating conditions at 20/spl deg/C, the measured pin-to-pin access time is 1.3 ns. The minimum write enable pulse width required is less than 1 ns, and the power dissipation, excluding the output buffers, is 650 mW at a clock rate of 100 MHz.
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A 1.3-ns 32-word by 32-bit three-Port BiCMOS Register file
Proceedings of IEEE Bipolar BiCMOS Circuits and Technology Meeting, 1Co-Authors: Chin-chieh Chao, B.a. WooleyAbstract:This paper describes a CMOS multiPort static memory cell that can be accessed through a low-voltage-swing read path. With this cell it is possible to achieve read access times comparable to those of pure bipolar memories while preserving the high density of CMOS memories. An experimental 32-word by 32-bit three-Port Register file has been designed and implemented using the cell. This circuit was fabricated in a 0.6-/spl mu/m BiCMOS technology and achieves a pin-to-pin access time of 1.3 ns at 20/spl deg/C.
Ji Lijiu - One of the best experts on this subject based on the ideXlab platform.
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Locally self-resetting CMOS in multi-Port Register file design
Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology 2004., 2004Co-Authors: Wang Fang, Jia Song, Ji LijiuAbstract:SRCMOS (self-resetting CMOS) is one kind of popular technique which can be used for designing high-speed circuits. This paper presents a new kind of locally self-resetting SRCMOS technique. According to the operational principle that the reset signal is generated by a mechanism local to its stage, the technique can realize high-speed circuits and has low design complexity. Based on the locally SRCMOS technique, the paper presents the design of a 32 word/spl times/64 bits 2write/6read eight-Port Register file. Using 1.8 V 0.18 /spl mu/m CMOS technology, simulation results show that the write access delay of the Register file is 700 ps, and read access delay is 910 ps.
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Design of high speed 2write/6read eight-Port Register file
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03, 2003Co-Authors: Wang Fang, Ji LijiuAbstract:This paper gives a delay model of the Register files which are made of multi-Port SRAM technology. Then we realized a 32wordt32 bit 2write/6read eight-Port Register files. During the realization, according to the presenting delay model, we present a grouping wordline method to reduce the delay time of Register files, also there are some structure modifying for the storage cells of Register files. With the 2.5 v 0.25 mm CMOS technology, simulation results show that delay time of the Register file is reduced by 11.5% than the Register file which hasn't adopted novel method.
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design of high speed 2write 6read eight Port Register file
International Conference on ASIC, 2003Co-Authors: Wang Fang, Ji LijiuAbstract:This paper gives a delay model of the Register files which are made of multi-Port SRAM technology. Then we realized a 32wordt32 bit 2write/6read eight-Port Register files. During the realization, according to the presenting delay model, we present a grouping wordline method to reduce the delay time of Register files, also there are some structure modifying for the storage cells of Register files. With the 2.5 v 0.25 mm CMOS technology, simulation results show that delay time of the Register file is reduced by 11.5% than the Register file which hasn't adopted novel method.
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Design of adiabatic multi-Port Register file
2005 6th International Conference on ASIC, 1Co-Authors: Wang Fang, Jia Song, Ji LijiuAbstract:The paper presents one kind of adiabatic driver for multi-Port Register file. Between decoder part and memory array, the adiabatic driver is added to reduce the power dissipation of word-line. At the same time, we also designed adiabatic sensing amplifier for Register file. Adiabatic circuits require trapezoidal wave or sinusoidal wave as inputs and outputs. But the Register file presented in this paper hasn't any requirement for inputs, so it can be easily used in embedded microprocessors. The experiment results show that the power dissipation of adiabatic Register file reduces 40% versus traditional Register file.
C.l. Chen - One of the best experts on this subject based on the ideXlab platform.
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a 640 ps 0 25 spl mu m cmos 16 spl times 64 b three Port Register file
IEEE Journal of Solid-state Circuits, 1997Co-Authors: R.l. Franch, C.l. ChenAbstract:We describe a 640-ps read access, 16-word by 64-b, three-Port Register file fabricated in 0.25-/spl mu/m effective channel length CMOS technology. It features the capability to perform a write followed by a read in the same cycle at frequencies above 500 MHz. High speed is achieved by using a novel cell and array structure. Static circuit design is used exclusively throughout the entire Register file and is optimized for high-speed operation. Measured results of the same-cycle read-after-write demonstrate Register file operations at 625 MHz. Additionally internal probe measurements of the read access path components are presented and compared with circuit simulations.
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A 640-ps, 0.25-/spl mu/m CMOS, 16/spl times/64-b three-Port Register file
IEEE Journal of Solid-State Circuits, 1997Co-Authors: R.l. Franch, C.l. ChenAbstract:We describe a 640-ps read access, 16-word by 64-b, three-Port Register file fabricated in 0.25-/spl mu/m effective channel length CMOS technology. It features the capability to perform a write followed by a read in the same cycle at frequencies above 500 MHz. High speed is achieved by using a novel cell and array structure. Static circuit design is used exclusively throughout the entire Register file and is optimized for high-speed operation. Measured results of the same-cycle read-after-write demonstrate Register file operations at 625 MHz. Additionally internal probe measurements of the read access path components are presented and compared with circuit simulations.
Chin-chieh Chao - One of the best experts on this subject based on the ideXlab platform.
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a 1 3 ns 32 word spl times 32 bit three Port bicmos Register file
IEEE Journal of Solid-state Circuits, 1996Co-Authors: Chin-chieh Chao, B.a. WooleyAbstract:This paper describes a CMOS multiPort static memory cell with which it is possible to use current-switching bipolar peripheral circuits to maintain small voltage swings throughout the read access path while retaining the high density of CMOS memory arrays. An experimental 32-word/spl times/32 bit three-Port Register file has been designed and implemented using this cell. The Register file was fabricated in a 0.6-/spl mu/m BiCMOS technology and operates from a single -3.3-V power supply with ECL-compatible I/O circuits. Under nominal operating conditions at 20/spl deg/C, the measured pin-to-pin access time is 1.3 ns. The minimum write enable pulse width required is less than 1 ns, and the power dissipation, excluding the output buffers, is 650 mW at a clock rate of 100 MHz.
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A 1.3-ns 32-word/spl times/32-bit three-Port BiCMOS Register file
IEEE Journal of Solid-State Circuits, 1996Co-Authors: Chin-chieh Chao, B.a. WooleyAbstract:This paper describes a CMOS multiPort static memory cell with which it is possible to use current-switching bipolar peripheral circuits to maintain small voltage swings throughout the read access path while retaining the high density of CMOS memory arrays. An experimental 32-word/spl times/32 bit three-Port Register file has been designed and implemented using this cell. The Register file was fabricated in a 0.6-/spl mu/m BiCMOS technology and operates from a single -3.3-V power supply with ECL-compatible I/O circuits. Under nominal operating conditions at 20/spl deg/C, the measured pin-to-pin access time is 1.3 ns. The minimum write enable pulse width required is less than 1 ns, and the power dissipation, excluding the output buffers, is 650 mW at a clock rate of 100 MHz.
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A 1.3-ns 32-word by 32-bit three-Port BiCMOS Register file
Proceedings of IEEE Bipolar BiCMOS Circuits and Technology Meeting, 1Co-Authors: Chin-chieh Chao, B.a. WooleyAbstract:This paper describes a CMOS multiPort static memory cell that can be accessed through a low-voltage-swing read path. With this cell it is possible to achieve read access times comparable to those of pure bipolar memories while preserving the high density of CMOS memories. An experimental 32-word by 32-bit three-Port Register file has been designed and implemented using the cell. This circuit was fabricated in a 0.6-/spl mu/m BiCMOS technology and achieves a pin-to-pin access time of 1.3 ns at 20/spl deg/C.
Wang Fang - One of the best experts on this subject based on the ideXlab platform.
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Locally self-resetting CMOS in multi-Port Register file design
Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology 2004., 2004Co-Authors: Wang Fang, Jia Song, Ji LijiuAbstract:SRCMOS (self-resetting CMOS) is one kind of popular technique which can be used for designing high-speed circuits. This paper presents a new kind of locally self-resetting SRCMOS technique. According to the operational principle that the reset signal is generated by a mechanism local to its stage, the technique can realize high-speed circuits and has low design complexity. Based on the locally SRCMOS technique, the paper presents the design of a 32 word/spl times/64 bits 2write/6read eight-Port Register file. Using 1.8 V 0.18 /spl mu/m CMOS technology, simulation results show that the write access delay of the Register file is 700 ps, and read access delay is 910 ps.
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Design of high speed 2write/6read eight-Port Register file
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03, 2003Co-Authors: Wang Fang, Ji LijiuAbstract:This paper gives a delay model of the Register files which are made of multi-Port SRAM technology. Then we realized a 32wordt32 bit 2write/6read eight-Port Register files. During the realization, according to the presenting delay model, we present a grouping wordline method to reduce the delay time of Register files, also there are some structure modifying for the storage cells of Register files. With the 2.5 v 0.25 mm CMOS technology, simulation results show that delay time of the Register file is reduced by 11.5% than the Register file which hasn't adopted novel method.
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design of high speed 2write 6read eight Port Register file
International Conference on ASIC, 2003Co-Authors: Wang Fang, Ji LijiuAbstract:This paper gives a delay model of the Register files which are made of multi-Port SRAM technology. Then we realized a 32wordt32 bit 2write/6read eight-Port Register files. During the realization, according to the presenting delay model, we present a grouping wordline method to reduce the delay time of Register files, also there are some structure modifying for the storage cells of Register files. With the 2.5 v 0.25 mm CMOS technology, simulation results show that delay time of the Register file is reduced by 11.5% than the Register file which hasn't adopted novel method.
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Design of adiabatic multi-Port Register file
2005 6th International Conference on ASIC, 1Co-Authors: Wang Fang, Jia Song, Ji LijiuAbstract:The paper presents one kind of adiabatic driver for multi-Port Register file. Between decoder part and memory array, the adiabatic driver is added to reduce the power dissipation of word-line. At the same time, we also designed adiabatic sensing amplifier for Register file. Adiabatic circuits require trapezoidal wave or sinusoidal wave as inputs and outputs. But the Register file presented in this paper hasn't any requirement for inputs, so it can be easily used in embedded microprocessors. The experiment results show that the power dissipation of adiabatic Register file reduces 40% versus traditional Register file.