The Experts below are selected from a list of 2805 Experts worldwide ranked by ideXlab platform
Javed I. Khan - One of the best experts on this subject based on the ideXlab platform.
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SAIL Based FIB Lookup in a Programmable Pipeline Based Linux Router
2019 IEEE 20th International Conference on High Performance Switching and Routing (HPSR), 2019Co-Authors: Md Iftakharul Islam, Javed I. KhanAbstract:This paper presents a Programmable Pipeline based Linux router. Here Linux kernel works as a control plane and the Programmable Pipeline works as a data plane. The Forwarding Information Base (FIB) lookup is performed using SAIL algorithm. SAIL consumes very large memory. Here we use population counting that reduces the memory consumption of SAIL by up to 80%. We have implemented SAIL in Linux kernel. We also have implemented SAIL using Domino programming language. Our implementation shows that a Programmable Pipeline can execute SAIL at line rate. We have evaluated our implementation with FIBs from real backbone routers. Our experimental results show that SAIL with population counting is suitable for implementing both dataplane and control plane of a high-speed router.
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HPSR - SAIL Based FIB Lookup in a Programmable Pipeline Based Linux Router
2019 IEEE 20th International Conference on High Performance Switching and Routing (HPSR), 2019Co-Authors: Iftakharul Islam, Javed I. KhanAbstract:This paper presents a Programmable Pipeline based Linux router. Here Linux kernel works as a control plane and the Programmable Pipeline works as a data plane. The Forwarding Information Base (FIB) lookup is performed using SAIL algorithm. SAIL consumes very large memory. Here we use population counting that reduces the memory consumption of SAIL by up to 80%. We have implemented SAIL in Linux kernel. We also have implemented SAIL using Domino programming language. Our implementation shows that a Programmable Pipeline can execute SAIL at line rate. We have evaluated our implementation with FIBs from real backbone routers. Our experimental results show that SAIL with population counting is suitable for implementing both dataplane and control plane of a high-speed router.
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leveraging domino to implement rcp in a stateful Programmable Pipeline
High Performance Switching and Routing, 2019Co-Authors: Iftakharul Islam, Javed I. KhanAbstract:RCP is a router-assisted congestion control mechanism where routers allocate a feedback rate to each flow. Here sender nodes regulate their sending rates based on the feedback rates received from the routers. An RCP router calculates the feedback rate based on the queue occupancy, spare capacity and the average RTT of the on-going flows. This is why, an RCP router needs to execute a stateful packet processing program in the dataplane. However stateful packet processing in a very highspeed (e.g. Tb/s) router is particularly challenging. Currently there is no real deployment of RCP, to the best of our knowledge. This paper presents an implementation of RCP protocol in a Programmable-Pipeline based router. We use Domino programming language to implement the dataplane. Domino is a domain specific language that allows us to develop a packet processing program as well as the hardware Pipeline on which the packet processing program would be executed. Domino programs are guaranteed to run at line rate. This is the first implementation of RCP using Domino. to the best of our knowledge.
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HPSR - Leveraging Domino to Implement RCP in a Stateful Programmable Pipeline
2019 IEEE 20th International Conference on High Performance Switching and Routing (HPSR), 2019Co-Authors: Iftakharul Islam, Javed I. KhanAbstract:RCP is a router-assisted congestion control mechanism where routers allocate a feedback rate to each flow. Here sender nodes regulate their sending rates based on the feedback rates received from the routers. An RCP router calculates the feedback rate based on the queue occupancy, spare capacity and the average RTT of the on-going flows. This is why, an RCP router needs to execute a stateful packet processing program in the dataplane. However stateful packet processing in a very highspeed (e.g. Tb/s) router is particularly challenging. Currently there is no real deployment of RCP, to the best of our knowledge. This paper presents an implementation of RCP protocol in a Programmable-Pipeline based router. We use Domino programming language to implement the dataplane. Domino is a domain specific language that allows us to develop a packet processing program as well as the hardware Pipeline on which the packet processing program would be executed. Domino programs are guaranteed to run at line rate. This is the first implementation of RCP using Domino. to the best of our knowledge.
Volker Ahlers - One of the best experts on this subject based on the ideXlab platform.
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SIGCSE - An extensible scene graph library for teaching computer graphics along the Programmable Pipeline (abstract only)
Proceedings of the 45th ACM technical symposium on Computer science education - SIGCSE '14, 2014Co-Authors: Volker AhlersAbstract:Computer graphics is a subject which is typically enjoyed by students and which has the potential to attract pupils to consider studying computer science. Although the programming methods used by computer graphics have significantly changed in recent years due to the integration of Programmable shaders into the graphics rendering Pipeline, a lot of computer graphics courses still start with the fixed-function Pipeline. In view of future applicability, however, it is desirable to teach students modern concepts of computer graphics from the beginning. One problem with teaching shader-based computer graphics is that a lot of technical tasks lie in the hand of the programmer: loading and compiling shader programs, managing buffer objects, defining transformations by means of matrices, etc. This poster presents a scene graph library which is fully based on the Programmable rendering Pipeline. It uses the OpenGL 3.2 core profile, which does not allow deprecated fixed-function functionality. The teaching approach combines the high-level abstraction of a scene graph with the low-level programming of shader cores, which are attributed to scene graph nodes. The presented scene graph library has a simple and clear structure and is extensible in order to let students implement advanced concepts taught in the lecture, like shadows or particle systems. Finally, the poster presents code samples, results of student projects, and student evaluation results.
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an extensible scene graph library for teaching computer graphics along the Programmable Pipeline abstract only
Technical Symposium on Computer Science Education, 2014Co-Authors: Volker AhlersAbstract:Computer graphics is a subject which is typically enjoyed by students and which has the potential to attract pupils to consider studying computer science. Although the programming methods used by computer graphics have significantly changed in recent years due to the integration of Programmable shaders into the graphics rendering Pipeline, a lot of computer graphics courses still start with the fixed-function Pipeline. In view of future applicability, however, it is desirable to teach students modern concepts of computer graphics from the beginning. One problem with teaching shader-based computer graphics is that a lot of technical tasks lie in the hand of the programmer: loading and compiling shader programs, managing buffer objects, defining transformations by means of matrices, etc. This poster presents a scene graph library which is fully based on the Programmable rendering Pipeline. It uses the OpenGL 3.2 core profile, which does not allow deprecated fixed-function functionality. The teaching approach combines the high-level abstraction of a scene graph with the low-level programming of shader cores, which are attributed to scene graph nodes. The presented scene graph library has a simple and clear structure and is extensible in order to let students implement advanced concepts taught in the lecture, like shadows or particle systems. Finally, the poster presents code samples, results of student projects, and student evaluation results.
John Golz - One of the best experts on this subject based on the ideXlab platform.
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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS
IEEE Journal of Solid-State Circuits, 2009Co-Authors: Peter Klim, William Reohr, David Dick, Gregory Fredeman, Gary Koch, Aditya Khargonekar, Hien M. Le, John Barth, Pamela Wilcox, John GolzAbstract:We describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation , a 4 Kb one-time-Programmable read-only memory (OTPROM) for redundancy and repair control, on-chip OTPROM programming voltage generation, clock generation and distribution, array built-in self-test circuitry (ABIST), user logic and pervasive logic. The eDRAM employs a Programmable Pipeline, achieving 1.8 ns latency, and features concurrent refresh capability.
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A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
2008 IEEE Symposium on VLSI Circuits, 2008Co-Authors: Peter Klim, William Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien Le, Aditya Khargonekar, John Barth, Pamela Wilcox, John GolzAbstract:We present a 1 MB cache subsystem that integrates 2 GHz embedded DRAM macros, charge pump circuits, a 4 Kb one-time-Programmable ROM, clock multipliers, and built-in self test circuitry, having a 36.5 GB/s peak system data-rate. The eDRAM employs a Programmable Pipeline, achieving a 1.8 ns latency.
Peter Klim - One of the best experts on this subject based on the ideXlab platform.
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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS
IEEE Journal of Solid-State Circuits, 2009Co-Authors: Peter Klim, William Reohr, David Dick, Gregory Fredeman, Gary Koch, Aditya Khargonekar, Hien M. Le, John Barth, Pamela Wilcox, John GolzAbstract:We describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation , a 4 Kb one-time-Programmable read-only memory (OTPROM) for redundancy and repair control, on-chip OTPROM programming voltage generation, clock generation and distribution, array built-in self-test circuitry (ABIST), user logic and pervasive logic. The eDRAM employs a Programmable Pipeline, achieving 1.8 ns latency, and features concurrent refresh capability.
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A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
2008 IEEE Symposium on VLSI Circuits, 2008Co-Authors: Peter Klim, William Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien Le, Aditya Khargonekar, John Barth, Pamela Wilcox, John GolzAbstract:We present a 1 MB cache subsystem that integrates 2 GHz embedded DRAM macros, charge pump circuits, a 4 Kb one-time-Programmable ROM, clock multipliers, and built-in self test circuitry, having a 36.5 GB/s peak system data-rate. The eDRAM employs a Programmable Pipeline, achieving a 1.8 ns latency.
Iftakharul Islam - One of the best experts on this subject based on the ideXlab platform.
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HPSR - SAIL Based FIB Lookup in a Programmable Pipeline Based Linux Router
2019 IEEE 20th International Conference on High Performance Switching and Routing (HPSR), 2019Co-Authors: Iftakharul Islam, Javed I. KhanAbstract:This paper presents a Programmable Pipeline based Linux router. Here Linux kernel works as a control plane and the Programmable Pipeline works as a data plane. The Forwarding Information Base (FIB) lookup is performed using SAIL algorithm. SAIL consumes very large memory. Here we use population counting that reduces the memory consumption of SAIL by up to 80%. We have implemented SAIL in Linux kernel. We also have implemented SAIL using Domino programming language. Our implementation shows that a Programmable Pipeline can execute SAIL at line rate. We have evaluated our implementation with FIBs from real backbone routers. Our experimental results show that SAIL with population counting is suitable for implementing both dataplane and control plane of a high-speed router.
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leveraging domino to implement rcp in a stateful Programmable Pipeline
High Performance Switching and Routing, 2019Co-Authors: Iftakharul Islam, Javed I. KhanAbstract:RCP is a router-assisted congestion control mechanism where routers allocate a feedback rate to each flow. Here sender nodes regulate their sending rates based on the feedback rates received from the routers. An RCP router calculates the feedback rate based on the queue occupancy, spare capacity and the average RTT of the on-going flows. This is why, an RCP router needs to execute a stateful packet processing program in the dataplane. However stateful packet processing in a very highspeed (e.g. Tb/s) router is particularly challenging. Currently there is no real deployment of RCP, to the best of our knowledge. This paper presents an implementation of RCP protocol in a Programmable-Pipeline based router. We use Domino programming language to implement the dataplane. Domino is a domain specific language that allows us to develop a packet processing program as well as the hardware Pipeline on which the packet processing program would be executed. Domino programs are guaranteed to run at line rate. This is the first implementation of RCP using Domino. to the best of our knowledge.
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HPSR - Leveraging Domino to Implement RCP in a Stateful Programmable Pipeline
2019 IEEE 20th International Conference on High Performance Switching and Routing (HPSR), 2019Co-Authors: Iftakharul Islam, Javed I. KhanAbstract:RCP is a router-assisted congestion control mechanism where routers allocate a feedback rate to each flow. Here sender nodes regulate their sending rates based on the feedback rates received from the routers. An RCP router calculates the feedback rate based on the queue occupancy, spare capacity and the average RTT of the on-going flows. This is why, an RCP router needs to execute a stateful packet processing program in the dataplane. However stateful packet processing in a very highspeed (e.g. Tb/s) router is particularly challenging. Currently there is no real deployment of RCP, to the best of our knowledge. This paper presents an implementation of RCP protocol in a Programmable-Pipeline based router. We use Domino programming language to implement the dataplane. Domino is a domain specific language that allows us to develop a packet processing program as well as the hardware Pipeline on which the packet processing program would be executed. Domino programs are guaranteed to run at line rate. This is the first implementation of RCP using Domino. to the best of our knowledge.