The Experts below are selected from a list of 303 Experts worldwide ranked by ideXlab platform
Gabriel M. Rebeiz - One of the best experts on this subject based on the ideXlab platform.
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A High-Linearity 76–85-GHz 16-Element 8-Transmit/8-Receive Phased-Array Chip With High Isolation and Flip-Chip Packaging
IEEE Transactions on Microwave Theory and Techniques, 2014Co-Authors: Bon-hyun Ku, Ozgur Inac, Michael Chang, Hyun-ho Yang, Gabriel M. RebeizAbstract:An SiGe transmit-Receive phased-array chip has been developed for automotive radar applications at 76-84 GHz. The chip is based on an all-RF beamforming approach and contains 8-transmit channels, 8-Receive channels, and a complete built-in-self-test system. Two high-linearity quadrature mixers with an input P1 dB of +2.5 dBm are used and allow simultaneous sum and difference patterns in the Receive mode. The chip operates in either a narrowband frequency-modulated continuous-wave (FMCW) mode or a wideband mode with > 2-GHz bandwidth. A high-linearity design results in an input P1 dB of -10 dBm (per channel), a system noise figure of 16-18 dB, and a transmit power is 4-5 dBm (per channel). The chip uses a controlled collapse chip connection (C4) bumping process and is flip-chipped on a low-cost printed-circuit board, and results in > 50-dB isolation between the transmit and Receive chains. To our knowledge, this work represents the state-of-the-art in terms of complexity at millimeter-wave frequencies and with simultaneous transmit and Receive Operation for high-performance FMCW radars.
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single and four element ka band transmit Receive phased array silicon rfics with 5 bit amplitude and phase control
IEEE Transactions on Microwave Theory and Techniques, 2009Co-Authors: Dong-woo Kang, Jeonggeun Kim, Byungwook Min, Gabriel M. RebeizAbstract:Ka-band SiGe BiCMOS single- and four-element phased arrays capable of both transmit and Receive Operation with 5-bit phase and amplitude control are presented. The design is based on the All-RF architecture with RF phase shifters and attenuators, and a 4:1 passive power combining/dividing network. The four-element array results in an average gain of ~ 0 dB per channel and a noise figure of 9.0 dB, and is designed to be placed behind III-V T/R modules. The rms phase error is 5.6° (5-bit Operation) and < 12.5° (4-bit Operation) over a 2 or 5 GHz instantaneous bandwidth, respectively, centered at around 36.5 GHz. In the Receive mode, the input P1dB is -16 dBm per channel (IIP3 of - 5.9 dBm), and in the transmit mode, the output P1dB is +4-5 dBm, all at 35-36 GHz. The measured isolation between the channels is better than 30 dB. The array maintained excellent phase characteristics up to 100°C with no change in the rms phase error. Also, ten different four-element phased arrays were tested (40 channels) and result in an rms gain variation of 0.5 dB at 34-39 GHz. The four-element array consumes 171 and 142 mW in the Tx and Rx modes from 1.8 V, and occupies an area of 2.0 × 2.02 mm2. To our knowledge, this is the smallest and lowest power consumption on-chip K ?-band phased-array to-date.
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A single-chip 36-38 GHz 4-element transmit/Receive phased-array with 5-bit amplitude and phase control
2009 IEEE MTT-S International Microwave Symposium Digest, 2009Co-Authors: Dong-woo Kang, Gabriel M. RebeizAbstract:A 4-element 36-38 GHz SiGe BiCMOS phased array capable of both transmit and Receive Operation with 5-bit phase and amplitude control is presented. The design is based on an All-RF approach and results in very small chip area and low power consumption. The array results in a measured average gain of ~0 dB per channel, a noise figure of 8-9 dB, P1dB of -16 dBm, and output P1dB of +4 dBm over an instantaneous bandwidth of 2 GHz. The array consumes 171 and 142 mW in the Tx and Rx modes from 1.8 V, and occupies an area of 2.0 times 2.02 mm2. To our knowledge, this is the smallest and lowest power consumption on-chip Ka-Band phased-array to-date.
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A single-chip 36-38 GHz 4-element transmit/Receive phased-array with 5-bit amplitude and phase control
2009 IEEE MTT-S International Microwave Symposium Digest, 2009Co-Authors: Dong-woo Kang, Gabriel M. RebeizAbstract:A 4-element 36-38 GHz SiGe BiCMOS phased array capable of both transmit and Receive Operation with 5-bit phase and amplitude control is presented. The design is based on an All-RF approach and results in very small chip area and low power consumption. The array results in a measured average gain of ∼0 dB per channel, a noise figure of 8–9 dB, P1dB of −16 dBm, and output P1dB of +4 dBm over an instantaneous bandwidth of 2 GHz. The array consumes 171 and 142 mW in the Tx and Rx modes from 1.8 V, and occupies an area of 2.0 × 2.02 mm2. To our knowledge, this is the smallest and lowest power consumption on-chip Ka-Band phased-array to-date.
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Single and Four-Element $Ka$-Band Transmit/Receive Phased-Array Silicon RFICs With 5-bit Amplitude and Phase Control
IEEE Transactions on Microwave Theory and Techniques, 2009Co-Authors: Dong-woo Kang, Gabriel M. RebeizAbstract:Ka-band SiGe BiCMOS single- and four-element phased arrays capable of both transmit and Receive Operation with 5-bit phase and amplitude control are presented. The design is based on the All-RF architecture with RF phase shifters and attenuators, and a 4:1 passive power combining/dividing network. The four-element array results in an average gain of ~ 0 dB per channel and a noise figure of 9.0 dB, and is designed to be placed behind III-V T/R modules. The rms phase error is 5.6° (5-bit Operation) and < 12.5° (4-bit Operation) over a 2 or 5 GHz instantaneous bandwidth, respectively, centered at around 36.5 GHz. In the Receive mode, the input P1dB is -16 dBm per channel (IIP3 of - 5.9 dBm), and in the transmit mode, the output P1dB is +4-5 dBm, all at 35-36 GHz. The measured isolation between the channels is better than 30 dB. The array maintained excellent phase characteristics up to 100°C with no change in the rms phase error. Also, ten different four-element phased arrays were tested (40 channels) and result in an rms gain variation of 0.5 dB at 34-39 GHz. The four-element array consumes 171 and 142 mW in the Tx and Rx modes from 1.8 V, and occupies an area of 2.0 × 2.02 mm2. To our knowledge, this is the smallest and lowest power consumption on-chip K ¿-band phased-array to-date.
Makoto Katagishi - One of the best experts on this subject based on the ideXlab platform.
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A 2.7-V GSM RF transceiver IC
IEEE Journal of Solid-State Circuits, 1997Co-Authors: Taizo Yamawaki, Masaru Kokubo, Kazuaki Hori, Takefumi Endou, Hiroshi Hagisawa, Tomio Furuya, Yoshimi Shimizu, Hiroaki Matsui, Kiyoshi Irie, Makoto KatagishiAbstract:A 2.7-V RF transceiver IC is intended for small, low-cost global system for mobile communications (GSM) handsets. This chip includes a quadrature modulator (QMOD) and an offset phase locked loop (OPLL) in the transmit path and a dual IF Receiver that consists of a low noise amplifier (LNA) with an active-bias circuit, two Gilbert-cell mixers, a programmable gain linear amplifier (PGA), and a quadrature demodulator (QDEM). The IC also contains frequency dividers with a very high frequency voltage controlled oscillator (VHF-VCO) to simplify the Receiver design. The system evaluation results are the phase error of 2.7° r.m.s. and the noise transmitted in the GSM receiving band of -163 dBc/Hz for transmitters and the reference sensitivity of -105 dBm for Receivers. Power-control functions are provided for independent transmit and Receive Operation. The IC is implemented by using bipolar technology with fT=15 GHz, r'bb=150 Ω, and 0.6-μm features
Taizo Yamawaki - One of the best experts on this subject based on the ideXlab platform.
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A 2.7-V GSM RF transceiver IC
IEEE Journal of Solid-State Circuits, 1997Co-Authors: Taizo Yamawaki, Masaru Kokubo, Kazuaki Hori, Takefumi Endou, Hiroshi Hagisawa, Tomio Furuya, Yoshimi Shimizu, Hiroaki Matsui, Kiyoshi Irie, Makoto KatagishiAbstract:A 2.7-V RF transceiver IC is intended for small, low-cost global system for mobile communications (GSM) handsets. This chip includes a quadrature modulator (QMOD) and an offset phase locked loop (OPLL) in the transmit path and a dual IF Receiver that consists of a low noise amplifier (LNA) with an active-bias circuit, two Gilbert-cell mixers, a programmable gain linear amplifier (PGA), and a quadrature demodulator (QDEM). The IC also contains frequency dividers with a very high frequency voltage controlled oscillator (VHF-VCO) to simplify the Receiver design. The system evaluation results are the phase error of 2.7° r.m.s. and the noise transmitted in the GSM receiving band of -163 dBc/Hz for transmitters and the reference sensitivity of -105 dBm for Receivers. Power-control functions are provided for independent transmit and Receive Operation. The IC is implemented by using bipolar technology with fT=15 GHz, r'bb=150 Ω, and 0.6-μm features
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A 2.7 V GSM RF transceiver IC
1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997Co-Authors: Kiyoshi Irie, Taizo Yamawaki, Masaru Kokubo, Hiroaki Matsui, T. Endo, K. Watanabe, J. HildersleyAbstract:This 2.7 V radio-frequency transceiver IC is intended for small, low-cost GSM handsets. All that is required to implement a GSM terminal radio section is this IC, a power amplifier module, dual-synthesizer IC, SAW filters, and other peripheral discrete components. This chip includes quadrature modulator phase-locked loop frequency translator with offset-mixer in the transmitter path, and a double-superhet Receiver that consists of LNA with active-bias circuits, two Gilbert cell mixers, programmable gain linear amplifier, and quadrature demodulator. The circuit also contains frequency dividers with on-chip VHF VCO to simplify 2nd LO design. Power control functions are provided for independent transmit and Receive Operation. The IC is implemented in pure bipolar technology with f/sub T/=15 GHz, r/sub bb/'=150 /spl Omega/, and 0.6 /spl mu/m features (0.6 /spl mu/m BiCMOS process).
Dong-woo Kang - One of the best experts on this subject based on the ideXlab platform.
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single and four element ka band transmit Receive phased array silicon rfics with 5 bit amplitude and phase control
IEEE Transactions on Microwave Theory and Techniques, 2009Co-Authors: Dong-woo Kang, Jeonggeun Kim, Byungwook Min, Gabriel M. RebeizAbstract:Ka-band SiGe BiCMOS single- and four-element phased arrays capable of both transmit and Receive Operation with 5-bit phase and amplitude control are presented. The design is based on the All-RF architecture with RF phase shifters and attenuators, and a 4:1 passive power combining/dividing network. The four-element array results in an average gain of ~ 0 dB per channel and a noise figure of 9.0 dB, and is designed to be placed behind III-V T/R modules. The rms phase error is 5.6° (5-bit Operation) and < 12.5° (4-bit Operation) over a 2 or 5 GHz instantaneous bandwidth, respectively, centered at around 36.5 GHz. In the Receive mode, the input P1dB is -16 dBm per channel (IIP3 of - 5.9 dBm), and in the transmit mode, the output P1dB is +4-5 dBm, all at 35-36 GHz. The measured isolation between the channels is better than 30 dB. The array maintained excellent phase characteristics up to 100°C with no change in the rms phase error. Also, ten different four-element phased arrays were tested (40 channels) and result in an rms gain variation of 0.5 dB at 34-39 GHz. The four-element array consumes 171 and 142 mW in the Tx and Rx modes from 1.8 V, and occupies an area of 2.0 × 2.02 mm2. To our knowledge, this is the smallest and lowest power consumption on-chip K ?-band phased-array to-date.
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A single-chip 36-38 GHz 4-element transmit/Receive phased-array with 5-bit amplitude and phase control
2009 IEEE MTT-S International Microwave Symposium Digest, 2009Co-Authors: Dong-woo Kang, Gabriel M. RebeizAbstract:A 4-element 36-38 GHz SiGe BiCMOS phased array capable of both transmit and Receive Operation with 5-bit phase and amplitude control is presented. The design is based on an All-RF approach and results in very small chip area and low power consumption. The array results in a measured average gain of ~0 dB per channel, a noise figure of 8-9 dB, P1dB of -16 dBm, and output P1dB of +4 dBm over an instantaneous bandwidth of 2 GHz. The array consumes 171 and 142 mW in the Tx and Rx modes from 1.8 V, and occupies an area of 2.0 times 2.02 mm2. To our knowledge, this is the smallest and lowest power consumption on-chip Ka-Band phased-array to-date.
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A single-chip 36-38 GHz 4-element transmit/Receive phased-array with 5-bit amplitude and phase control
2009 IEEE MTT-S International Microwave Symposium Digest, 2009Co-Authors: Dong-woo Kang, Gabriel M. RebeizAbstract:A 4-element 36-38 GHz SiGe BiCMOS phased array capable of both transmit and Receive Operation with 5-bit phase and amplitude control is presented. The design is based on an All-RF approach and results in very small chip area and low power consumption. The array results in a measured average gain of ∼0 dB per channel, a noise figure of 8–9 dB, P1dB of −16 dBm, and output P1dB of +4 dBm over an instantaneous bandwidth of 2 GHz. The array consumes 171 and 142 mW in the Tx and Rx modes from 1.8 V, and occupies an area of 2.0 × 2.02 mm2. To our knowledge, this is the smallest and lowest power consumption on-chip Ka-Band phased-array to-date.
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Single and Four-Element $Ka$-Band Transmit/Receive Phased-Array Silicon RFICs With 5-bit Amplitude and Phase Control
IEEE Transactions on Microwave Theory and Techniques, 2009Co-Authors: Dong-woo Kang, Gabriel M. RebeizAbstract:Ka-band SiGe BiCMOS single- and four-element phased arrays capable of both transmit and Receive Operation with 5-bit phase and amplitude control are presented. The design is based on the All-RF architecture with RF phase shifters and attenuators, and a 4:1 passive power combining/dividing network. The four-element array results in an average gain of ~ 0 dB per channel and a noise figure of 9.0 dB, and is designed to be placed behind III-V T/R modules. The rms phase error is 5.6° (5-bit Operation) and < 12.5° (4-bit Operation) over a 2 or 5 GHz instantaneous bandwidth, respectively, centered at around 36.5 GHz. In the Receive mode, the input P1dB is -16 dBm per channel (IIP3 of - 5.9 dBm), and in the transmit mode, the output P1dB is +4-5 dBm, all at 35-36 GHz. The measured isolation between the channels is better than 30 dB. The array maintained excellent phase characteristics up to 100°C with no change in the rms phase error. Also, ten different four-element phased arrays were tested (40 channels) and result in an rms gain variation of 0.5 dB at 34-39 GHz. The four-element array consumes 171 and 142 mW in the Tx and Rx modes from 1.8 V, and occupies an area of 2.0 × 2.02 mm2. To our knowledge, this is the smallest and lowest power consumption on-chip K ¿-band phased-array to-date.
Kiyoshi Irie - One of the best experts on this subject based on the ideXlab platform.
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A 2.7-V GSM RF transceiver IC
IEEE Journal of Solid-State Circuits, 1997Co-Authors: Taizo Yamawaki, Masaru Kokubo, Kazuaki Hori, Takefumi Endou, Hiroshi Hagisawa, Tomio Furuya, Yoshimi Shimizu, Hiroaki Matsui, Kiyoshi Irie, Makoto KatagishiAbstract:A 2.7-V RF transceiver IC is intended for small, low-cost global system for mobile communications (GSM) handsets. This chip includes a quadrature modulator (QMOD) and an offset phase locked loop (OPLL) in the transmit path and a dual IF Receiver that consists of a low noise amplifier (LNA) with an active-bias circuit, two Gilbert-cell mixers, a programmable gain linear amplifier (PGA), and a quadrature demodulator (QDEM). The IC also contains frequency dividers with a very high frequency voltage controlled oscillator (VHF-VCO) to simplify the Receiver design. The system evaluation results are the phase error of 2.7° r.m.s. and the noise transmitted in the GSM receiving band of -163 dBc/Hz for transmitters and the reference sensitivity of -105 dBm for Receivers. Power-control functions are provided for independent transmit and Receive Operation. The IC is implemented by using bipolar technology with fT=15 GHz, r'bb=150 Ω, and 0.6-μm features
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A 2.7 V GSM RF transceiver IC
1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997Co-Authors: Kiyoshi Irie, Taizo Yamawaki, Masaru Kokubo, Hiroaki Matsui, T. Endo, K. Watanabe, J. HildersleyAbstract:This 2.7 V radio-frequency transceiver IC is intended for small, low-cost GSM handsets. All that is required to implement a GSM terminal radio section is this IC, a power amplifier module, dual-synthesizer IC, SAW filters, and other peripheral discrete components. This chip includes quadrature modulator phase-locked loop frequency translator with offset-mixer in the transmitter path, and a double-superhet Receiver that consists of LNA with active-bias circuits, two Gilbert cell mixers, programmable gain linear amplifier, and quadrature demodulator. The circuit also contains frequency dividers with on-chip VHF VCO to simplify 2nd LO design. Power control functions are provided for independent transmit and Receive Operation. The IC is implemented in pure bipolar technology with f/sub T/=15 GHz, r/sub bb/'=150 /spl Omega/, and 0.6 /spl mu/m features (0.6 /spl mu/m BiCMOS process).
