The Experts below are selected from a list of 12777 Experts worldwide ranked by ideXlab platform
Seonghwan Cho - One of the best experts on this subject based on the ideXlab platform.
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ISSCC - 5.10 A 4.7MHz 53μW fully differential CMOS Reference Clock oscillator with −22dB worst-case PSNR for miniaturized SoCs
2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015Co-Authors: Junghyup Lee, Pyoungwon Park, Seonghwan ChoAbstract:Low-power CMOS Reference Clock oscillators have been widely used in miniaturized SoCs for emerging microsystems such as implantable biomedical devices and smart sensors [1-3]. In such SoCs, as the supply voltage shrinks and the level of analog and digital circuit integration increases to meet rigorous power and area constraints, the noise from other blocks (especially digital blocks) couples through supply and ground lines and poses a serious threat to the performance of CMOS Reference Clock oscillators.
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A 10MHz 80μW 67 ppm/°C CMOS Reference Clock oscillator with a temperature compensated feedback loop in 0.18μm CMOS
2009Co-Authors: Junghyup Lee, Seonghwan ChoAbstract:A 10MHz, 80μW CMOS Reference Clock oscillator is presented in 0.18μm CMOS. The proposed oscillator employs a supply-regulated ring-oscillator in a temperature compensated feedback loop, which minimizes the frequency sensitivity to supply and temperature variations. The Clock oscillator achieves frequency variation of less than ±0.05% against supply variation of 1.2V ~ 3V and ±0.4% against temperature variation of −20°C ~ 120°C. In addition, low power consumption is achieved by using sub-threshold bias circuits.
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a 10mhz 80μw 67 ppm c cmos Reference Clock oscillator with a temperature compensated feedback loop in 0 18μm cmos
Symposium on VLSI Circuits, 2009Co-Authors: Junghyup Lee, Seonghwan ChoAbstract:A 10MHz, 80μW CMOS Reference Clock oscillator is presented in 0.18μm CMOS. The proposed oscillator employs a supply-regulated ring-oscillator in a temperature compensated feedback loop, which minimizes the frequency sensitivity to supply and temperature variations. The Clock oscillator achieves frequency variation of less than ±0.05% against supply variation of 1.2V ~ 3V and ±0.4% against temperature variation of −20°C ~ 120°C. In addition, low power consumption is achieved by using sub-threshold bias circuits.
J. Wilstrup - One of the best experts on this subject based on the ideXlab platform.
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Transfer functions for the Reference Clock jitter in a serial link: theory and applications
2005Co-Authors: A. Martwick, G Talbot, J. WilstrupAbstract:Transfer functions for the Reference Clock jitter in a serial link such as the PCI express 100 MHz Reference Clock are established for various Clock and data recovery circuits (CDRCs). In addition, mathematical interrelationships between phase, period, and cycle-to-cycle jitter are established and phase jitter is used with the jitter transfer function. Numerical simulations are carried out for these transfer functions. Relevant eye-closure/total jitter at a certain bit error rate (BER) level for the receiver is estimated by applying these jitter transfer functions to the measured phase jitter of the Reference Clock over a range of transfer function parameters. Implications of this new development to serial link Reference Clock testing and specification formulation are discussed.
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ITC - Transfer functions for the Reference Clock jitter in a serial link: theory and applications
2004 International Conferce on Test, 1Co-Authors: A. Martwick, G Talbot, J. WilstrupAbstract:Transfer functions for the Reference Clock jitter in a serial link such as the PCI express 100 MHz Reference Clock are established for various Clock and data recovery circuits (CDRCs). In addition, mathematical interrelationships between phase, period, and cycle-to-cycle jitter are established and phase jitter is used with the jitter transfer function. Numerical simulations are carried out for these transfer functions. Relevant eye-closure/total jitter at a certain bit error rate (BER) level for the receiver is estimated by applying these jitter transfer functions to the measured phase jitter of the Reference Clock over a range of transfer function parameters. Implications of this new development to serial link Reference Clock testing and specification formulation are discussed.
Junghyup Lee - One of the best experts on this subject based on the ideXlab platform.
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ISSCC - 5.10 A 4.7MHz 53μW fully differential CMOS Reference Clock oscillator with −22dB worst-case PSNR for miniaturized SoCs
2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015Co-Authors: Junghyup Lee, Pyoungwon Park, Seonghwan ChoAbstract:Low-power CMOS Reference Clock oscillators have been widely used in miniaturized SoCs for emerging microsystems such as implantable biomedical devices and smart sensors [1-3]. In such SoCs, as the supply voltage shrinks and the level of analog and digital circuit integration increases to meet rigorous power and area constraints, the noise from other blocks (especially digital blocks) couples through supply and ground lines and poses a serious threat to the performance of CMOS Reference Clock oscillators.
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A 10MHz 80μW 67 ppm/°C CMOS Reference Clock oscillator with a temperature compensated feedback loop in 0.18μm CMOS
2009Co-Authors: Junghyup Lee, Seonghwan ChoAbstract:A 10MHz, 80μW CMOS Reference Clock oscillator is presented in 0.18μm CMOS. The proposed oscillator employs a supply-regulated ring-oscillator in a temperature compensated feedback loop, which minimizes the frequency sensitivity to supply and temperature variations. The Clock oscillator achieves frequency variation of less than ±0.05% against supply variation of 1.2V ~ 3V and ±0.4% against temperature variation of −20°C ~ 120°C. In addition, low power consumption is achieved by using sub-threshold bias circuits.
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a 10mhz 80μw 67 ppm c cmos Reference Clock oscillator with a temperature compensated feedback loop in 0 18μm cmos
Symposium on VLSI Circuits, 2009Co-Authors: Junghyup Lee, Seonghwan ChoAbstract:A 10MHz, 80μW CMOS Reference Clock oscillator is presented in 0.18μm CMOS. The proposed oscillator employs a supply-regulated ring-oscillator in a temperature compensated feedback loop, which minimizes the frequency sensitivity to supply and temperature variations. The Clock oscillator achieves frequency variation of less than ±0.05% against supply variation of 1.2V ~ 3V and ±0.4% against temperature variation of −20°C ~ 120°C. In addition, low power consumption is achieved by using sub-threshold bias circuits.
Bram Nauta - One of the best experts on this subject based on the ideXlab platform.
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a 2 2ghz sub sampling pll with 0 16ps rms jitter and 125dbc hz in band phase noise at 700µw loop components power
Symposium on VLSI Circuits, 2010Co-Authors: Xiang Gao, Eric A M Klumperink, Gerard G Socci, Mounir Bohsali, Bram NautaAbstract:A divider-less PLL exploits a phase detector that directly samples the VCO with a Reference Clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <−56dBc. A modified inverter with low short-circuit current acts as a power efficient Reference Clock buffer. The 2.2GHz PLL in 0.18µm CMOS achieves −125dBc/Hz in-band phase noise with only 700µW loop-components power.
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A 2.2GHz sub-sampling PLL with 0.16ps rms jitter and −125dBc/Hz in-band phase noise at 700µW loop-components power
2010 Symposium on VLSI Circuits, 2010Co-Authors: Xiang Gao, Eric A M Klumperink, Gerard G Socci, Mounir Bohsali, Bram NautaAbstract:A divider-less PLL exploits a phase detector that directly samples the VCO with a Reference Clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur
Hong Zhang - One of the best experts on this subject based on the ideXlab platform.
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A +0.66/−0.73 °C Inaccuracy, 1.99-μW Time-Domain CMOS Temperature Sensor With Second-Order ΔΣ Modulator and On-Chip Reference Clock
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020Co-Authors: Yang Chen, Zihao Jiao, Weijun Guan, Quan Sun, Xiaofei Wang, Ruizhi Zhang, Hong ZhangAbstract:This paper presents a compact and low-power time-domain CMOS temperature sensor intended for Internet of Things. To eliminate the off-chip Reference Clock that is commonly needed for time-domain CMOS temperature sensors, a precise on-chip Reference Clock is designed to measure the temperature-dependent delay generated by an inverter chain with even stages. In the Reference Clock circuit, a relaxation oscillator showing discharging phases with negative temperature coefficient (TC) is designed, which are compensated by 2 identical inverter-chains with positive-TC delay, resulting in a Reference Clock with nearly temperature-independent pulse width and period. In addition, a $2^{{\text {nd}}}$ -order hybrid time-voltage delta-sigma ( $\Delta \Sigma $ ) modulator with feedforward path is proposed to quantize the temperature-dependent delay of the main inverter chain, achieving 100-mK resolution only in about 25-ms conversion time. Fabricated in 0.18- $\mu \text{m}$ CMOS, measurement results show that the best (worst)-case temperature accuracy of the Clock’s Reference time is ±0.015% (±0.055%) and the temperature sensor achieves a maximum inaccuracy of +0.66/−0.73 °C from −20 °C to −80 °C. The prototype occupies 0.45-mm2 chip area and consumes 1.99- $\mu \text{W}$ from a 1.8-V supply at room temperature.
