The Experts below are selected from a list of 28812 Experts worldwide ranked by ideXlab platform
Sachin S Sapatnekar - One of the best experts on this subject based on the ideXlab platform.
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adaptive techniques for overcoming performance degradation due to aging in cmos circuits
IEEE Transactions on Very Large Scale Integration Systems, 2011Co-Authors: Sanjay V. Kumar, Chris H. Kim, Sachin S SapatnekarAbstract:Negative bias temperature instability (NBTI) in pMOS transistors has become a major Reliability Concern in present-day digital circuit design. Further, with the recent introduction of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in nMOS transistors, has also reached significant levels. Consequently, designs are required to build in substantial guardbands in order to guarantee reliable operation over the lifetime of a chip, and these involve large area and power overheads. In this paper, we begin by proposing the use of adaptive body bias (ABB) and adaptive supply voltage (ASV) to maintain optimal performance of an aged circuit, and demonstrate its advantages over a guard banding technique such as synthesis. We then present a hybrid approach, utilizing the merits of both ABB and synthesis, to ensure that the resultant circuit meets the performance constraints over its lifetime, and has a minimal area and power overhead, as compared with a nominally designed circuit.
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adaptive techniques for overcoming performance degradation due to aging in digital circuits
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Sanjay V. Kumar, Sachin S SapatnekarAbstract:Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major Reliability Concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, Positive Bias Temperature Instability (PBTI), the dual effect in NMOS transistors has also reached significant levels. Consequently, designers are required to build in substantial guard-bands into their designs, leading to large area and power overheads, in order to guarantee reliable operation over the lifetime of a chip. We propose a guard-banding technique based on adaptive body bias (ABB) and adaptive supply voltage (ASV), to recover the performance of an aged circuit, and compare its merits over previous approaches.
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nbti aware synthesis of digital circuits
Design Automation Conference, 2007Co-Authors: Sanjay V. Kumar, Sachin S SapatnekarAbstract:Negative bias temperature instability (NBTI) in PMOS transistors has become a major Reliability Concern in nanometer scale design, causing the temporal degradation of the threshold voltage of the PMOS transistors, and the delay of digital circuits. A novel method to characterize the delay of every gate in the standard cell library, as a function of the signal probability of each of its inputs, is developed. Accordingly, a technology mapping technique that incorporates the NBTI stress and recovery effects, in order to ensure optimal performance of the circuit, during its entire lifetime, is presented. Our technique, demonstrated over 65 nm benchmarks shows an average of 10 % area recovery, and 12 % power savings, as against a pessimistic method that assumes constant stress on all PMOS transistors in the design.
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an analytical model for negative bias temperature instability
International Conference on Computer Aided Design, 2006Co-Authors: Sanjay V. Kumar, Chris H. Kim, Sachin S SapatnekarAbstract:Negative bias temperature instability (NBTI) in PMOS transistors has become a significant Reliability Concern in present day digital circuit design. With continued scaling, the effect of NBTI has rapidly grown in prominence, forcing designers to resort to a pessimistic design style using guard-banding. Since NBTI is strongly dependent on the time for which the PMOS device is stressed, different gates in a combinational circuit experience varying extents of delay degradation. This has necessitated a mechanism of quantizing the gate-delay degradation, to pave the way for improved design strategies. Our work addresses this issue by providing a procedure for determining the amount of delay degradation of a circuit due to NBTI. An analytical model for NBTI is derived using the framework of the reaction-diffusion model, and a mathematical proof for the widely observed phenomenon of frequency independence is provided. Simulations on ISCAS benchmarks under a 70nm technology show that NBTI causes a delay degradation of about 8% in combinational logic based circuits after 10 years (ap 3 times 108s)
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an analytical model for negative bias temperature instability
International Conference on Computer Aided Design, 2006Co-Authors: Sanjay V. Kumar, Chris H. Kim, Sachin S SapatnekarAbstract:Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant Reliability Concern in present day digital circuit design. With continued scaling, the effect of NBTI has rapidly grown in prominence, forcing designers to resort to a pessimistic design style using guard-banding. Since NBTI is strongly dependent on the time for which the PMOS device is stressed, different gates in a combinational circuit experience varying extents of delay degradation. This has necessitated a mechanism of quantizing the gate-delay degradation, to pave the way for improved design strategies. Our work addresses this issue by providing a procedure for determining the amount of delay degradation of a circuit due to NBTI. An analytical model for NBTI is derived using the framework of the Reaction-Diffusion model, and a mathematical proof for the widely observed phenomenon of frequency independence is provided. Simulations on ISCAS benchmarks under a 70nm technology show that NBTI causes a delay degradation of about 8% in combinational logic based circuits after 10 years (a 3 x 108s).
Sanjay V. Kumar - One of the best experts on this subject based on the ideXlab platform.
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adaptive techniques for overcoming performance degradation due to aging in cmos circuits
IEEE Transactions on Very Large Scale Integration Systems, 2011Co-Authors: Sanjay V. Kumar, Chris H. Kim, Sachin S SapatnekarAbstract:Negative bias temperature instability (NBTI) in pMOS transistors has become a major Reliability Concern in present-day digital circuit design. Further, with the recent introduction of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in nMOS transistors, has also reached significant levels. Consequently, designs are required to build in substantial guardbands in order to guarantee reliable operation over the lifetime of a chip, and these involve large area and power overheads. In this paper, we begin by proposing the use of adaptive body bias (ABB) and adaptive supply voltage (ASV) to maintain optimal performance of an aged circuit, and demonstrate its advantages over a guard banding technique such as synthesis. We then present a hybrid approach, utilizing the merits of both ABB and synthesis, to ensure that the resultant circuit meets the performance constraints over its lifetime, and has a minimal area and power overhead, as compared with a nominally designed circuit.
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adaptive techniques for overcoming performance degradation due to aging in digital circuits
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Sanjay V. Kumar, Sachin S SapatnekarAbstract:Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major Reliability Concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, Positive Bias Temperature Instability (PBTI), the dual effect in NMOS transistors has also reached significant levels. Consequently, designers are required to build in substantial guard-bands into their designs, leading to large area and power overheads, in order to guarantee reliable operation over the lifetime of a chip. We propose a guard-banding technique based on adaptive body bias (ABB) and adaptive supply voltage (ASV), to recover the performance of an aged circuit, and compare its merits over previous approaches.
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nbti aware synthesis of digital circuits
Design Automation Conference, 2007Co-Authors: Sanjay V. Kumar, Sachin S SapatnekarAbstract:Negative bias temperature instability (NBTI) in PMOS transistors has become a major Reliability Concern in nanometer scale design, causing the temporal degradation of the threshold voltage of the PMOS transistors, and the delay of digital circuits. A novel method to characterize the delay of every gate in the standard cell library, as a function of the signal probability of each of its inputs, is developed. Accordingly, a technology mapping technique that incorporates the NBTI stress and recovery effects, in order to ensure optimal performance of the circuit, during its entire lifetime, is presented. Our technique, demonstrated over 65 nm benchmarks shows an average of 10 % area recovery, and 12 % power savings, as against a pessimistic method that assumes constant stress on all PMOS transistors in the design.
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an analytical model for negative bias temperature instability
International Conference on Computer Aided Design, 2006Co-Authors: Sanjay V. Kumar, Chris H. Kim, Sachin S SapatnekarAbstract:Negative bias temperature instability (NBTI) in PMOS transistors has become a significant Reliability Concern in present day digital circuit design. With continued scaling, the effect of NBTI has rapidly grown in prominence, forcing designers to resort to a pessimistic design style using guard-banding. Since NBTI is strongly dependent on the time for which the PMOS device is stressed, different gates in a combinational circuit experience varying extents of delay degradation. This has necessitated a mechanism of quantizing the gate-delay degradation, to pave the way for improved design strategies. Our work addresses this issue by providing a procedure for determining the amount of delay degradation of a circuit due to NBTI. An analytical model for NBTI is derived using the framework of the reaction-diffusion model, and a mathematical proof for the widely observed phenomenon of frequency independence is provided. Simulations on ISCAS benchmarks under a 70nm technology show that NBTI causes a delay degradation of about 8% in combinational logic based circuits after 10 years (ap 3 times 108s)
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an analytical model for negative bias temperature instability
International Conference on Computer Aided Design, 2006Co-Authors: Sanjay V. Kumar, Chris H. Kim, Sachin S SapatnekarAbstract:Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant Reliability Concern in present day digital circuit design. With continued scaling, the effect of NBTI has rapidly grown in prominence, forcing designers to resort to a pessimistic design style using guard-banding. Since NBTI is strongly dependent on the time for which the PMOS device is stressed, different gates in a combinational circuit experience varying extents of delay degradation. This has necessitated a mechanism of quantizing the gate-delay degradation, to pave the way for improved design strategies. Our work addresses this issue by providing a procedure for determining the amount of delay degradation of a circuit due to NBTI. An analytical model for NBTI is derived using the framework of the Reaction-Diffusion model, and a mathematical proof for the widely observed phenomenon of frequency independence is provided. Simulations on ISCAS benchmarks under a 70nm technology show that NBTI causes a delay degradation of about 8% in combinational logic based circuits after 10 years (a 3 x 108s).
Yu Cao - One of the best experts on this subject based on the ideXlab platform.
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Compact modeling and simulation of circuit Reliability for 65-nm CMOS technology
IEEE Transactions on Device and Materials Reliability, 2007Co-Authors: Wenping Wang, Anand T. Krishnan, Rakesh Vattikonda, Vijay Reddy, Srikanth Krishnan, Yu CaoAbstract:Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading Reliability Concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant Reliability Concern, and the impact of CHC on circuit performance is relatively small.
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modeling and minimization of pmos nbti effect for robust nanometer design
Design Automation Conference, 2006Co-Authors: Rakesh Vattikonda, Wenping Wang, Yu CaoAbstract:Negative bias temperature instability (NBTI) has become the dominant Reliability Concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the degradation of NBTI in both static and dynamic operations. Model scalability and generality are comprehensively verified with experimental data over a wide range of process and bias conditions. By implementing the new model into SPICE for an industrial 90nm technology, key insights are obtained for the development of robust design solutions: (1) the most effective techniques to mitigate the NBTI degradation are V/sub DD/ tuning, PMOS sizing, and reducing the duty cycle; (2) an optimal V/sub DD/ exists to minimize the degradation of circuit performance; (3) tuning gate length or the switching frequency has little impact on the NBTI effect; (4) a new switching scenario is identified for worst case timing analysis during NBTI stress.
Muhammad A Alam - One of the best experts on this subject based on the ideXlab platform.
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theory of charging and charge transport in intermediate thickness dielectrics and its implications for characterization and Reliability
Journal of Applied Physics, 2012Co-Authors: Sambit Palit, Muhammad A AlamAbstract:Thin film dielectrics have broad applications, and the performance degradation due to charge trapping in these thin films is an important and pervasive Reliability Concern. It has been presumed since the 1960s that current transport in intermediate-thickness (IT) oxides (∼10–100 nm) can be described by Frenkel-Poole (FP) conduction (originally developed for ∼mm-thick films) and algorithms based on the FP theory can be used to extract defect energy levels and charging-limited lifetime. In this paper, we review the published results to show that the presumption of FP-dominated current in IT oxides is incorrect, and therefore, the methods to extract trap-depths to predict lifetime should be revised. We generalize/adapt the bulk FP current conduction model by including additional tunneling-based current injection. Steady state characteristics are obtained by a flux balance between contacts and the IT oxide. An analytical approximation of the generalized FP model yields a steady state leakage current J ∝ exp(−...
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strategies for dynamic soft landing in capacitive microelectromechanical switches
Applied Physics Letters, 2011Co-Authors: Ankit Jain, Pradeep R Nair, Muhammad A AlamAbstract:Electromechanical dielectric degradation associated with the hard landing of movable electrode is a technology-inhibiting Reliability Concern for capacitive RF-MEMS switches. In this letter, we propose two schemes for dynamic soft-landing that obviate the need for external feedback circuitry. Instead, the proposed resistive and capacitive braking schemes can reduce impact velocity significantly without compromising other performance characteristics like pull-in voltage and pull-in time. Resistive braking is achieved by inserting a resistance in series with the voltage source whereas capacitive braking requires patterning of the electrode or the dielectric. Our results have important implications to the design and optimization of Reliability aware electrostatically actuated MEMS switches.
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a comprehensive model for pmos nbti degradation recent progress
Microelectronics Reliability, 2007Co-Authors: Muhammad A Alam, H Kufluoglu, D Varghese, S MahapatraAbstract:Abstract Negative bias temperature instability (NBTI) is a well-known Reliability Concern for PMOS transistors. We review the literature to find seven key experimental features of NBTI degradation. These features appear mutually inconsistent and have often defied easy interpretation. By reformulating the Reaction–Diffusion model in a particularly simple form, we show that these seven apparently contradictory features of NBTI actually reflect different facets of the same underlying physical mechanism.
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a comprehensive model of pmos nbti degradation
Microelectronics Reliability, 2005Co-Authors: Muhammad A Alam, S MahapatraAbstract:Abstract Negative bias temperature instability has become an important Reliability Concern for ultra-scaled Silicon IC technology with significant implications for both analog and digital circuit design. In this paper, we construct a comprehensive model for NBTI phenomena within the framework of the standard reaction–diffusion model. We demonstrate how to solve the reaction–diffusion equations in a way that emphasizes the physical aspects of the degradation process and allows easy generalization of the existing work. We also augment this basic reaction–diffusion model by including the temperature and field-dependence of the NBTI phenomena so that Reliability projections can be made under arbitrary circuit operating conditions.
P Chaparala - One of the best experts on this subject based on the ideXlab platform.
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a new fast switching nbti characterization method that determines subthreshold slope degradation
IEEE Transactions on Device and Materials Reliability, 2009Co-Authors: D Brisbin, P ChaparalaAbstract:For PMOSFET devices, negative bias temperature instability (NBTI) is a serious Reliability Concern. Because of recovery effects, careful stress and measurement methods must be used to determine threshold voltage degradation. These methods typically assume that mobility and subthreshold slope (SubSlp) degradation are minimal. Recent papers have pointed out that this assumption may not be valid. This paper discusses for the first time a unique fast-switching NBTI measurement technique that alternates between two VGS measurement conditions to determine the SubSlp versus stress time. From these measurements, the effect of SubSlp degradation on VT degradation can be accurately determined, and results are compared to the standard techniques.
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the effect of the subthreshold slope degradation on nbti device characterization
International Integrated Reliability Workshop, 2008Co-Authors: D Brisbin, P ChaparalaAbstract:For PMOSFET devices NBTI is a serious Reliability Concern. Because of recovery effects careful stress and measurement methods must be used to determine threshold voltage degradation. These methods assume that mobility and subthreshold slope degradation are minimal. Recent papers have pointed out that this assumption may not be valid. This paper discusses for the first time a unique fast switching NBTI measurement technique that alternates between two VGS measurement conditions to determine the subthreshold slope vs. stress time. From these measurements the effect of subthreshold slope degradation on VT degradation can be accurately determined and results compared to the standard techniques. In, addition, this work also introduces an improved NBTI fast switching test methodology to complement the pending NBTI JEDEC testing standard.