The Experts below are selected from a list of 288 Experts worldwide ranked by ideXlab platform
Songcheol Hong - One of the best experts on this subject based on the ideXlab platform.
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A study on magnetic field Repeater in wireless power transfer
IEEE Transactions on Industrial Electronics, 2013Co-Authors: Dukju Ahn, Songcheol HongAbstract:It is shown that the distance of wireless power transfer is significantly increased by placing intermediate resonators (Repeaters) between transmitter and receiver. The guidelines are provided to use the Repeaters effectively. We first briefly review how the Repeaters enhance the transfer distance. Next, the aspect of resonant frequency splitting is studied separately both for even and odd numbers of Repeaters. The transferred power, efficiency, and output impedance phase are evaluated for each Repeater configuration. These provide the guidelines to select the optimum Repeater positions and numbers. We also propose and study a new kind of Repeater which can be placed (biased) even in the vicinity of transmitter or receiver. This increases the flexibility in choosing the Repeater position. The net effect of such biased Repeater is approximately doubling the effective coupling coefficient between transmitter and receiver. Experimental results are provided to prove the concepts.
Ian H. White - One of the best experts on this subject based on the ideXlab platform.
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Passive UHF RFID interrogation system using wireless RFID Repeater nodes
2013 IEEE International Conference on RFID (RFID), 2013Co-Authors: Sithamparanathan Sabesan, Michael Crisp, Richard V. Penty, Ian H. WhiteAbstract:This paper presents a new wireless radio frequency identification (RFID) Repeater system, facilitating remote interrogation without the need for arrays of wired antennas, despite using entirely passive, low-cost ultra high frequency (UHF) RFID tags. The proposed system comprises a master RFID reader with both transmit and receive functions, and multiple RFID Repeaters to receive, amplify and retransmit tag-to-reader and reader-to-tag communications. This expands the area over which the master RFID reader may provide coverage for a given maximum transmit power at each antenna. We first demonstrate a single hop wireless Repeater system to allow similar read performance to a standard commercial passive UHF RFID reader. Finally, a proof of principle system demonstrates that a single wireless Repeater node can allow an extension in range.
Eby G Friedman - One of the best experts on this subject based on the ideXlab platform.
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Optimum wire sizing of RLC interconnect with Repeaters
Integration, 2004Co-Authors: Magdy A. El-moursy, Eby G FriedmanAbstract:Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be considered in determining the optimum number and size of the Repeaters driving a line. The optimum Repeater system uses uniform Repeater insertion in order to achieve the minimum propagation delay. A tradeoff exists, however, between the transient power dissipation and the minimum propagation delay in sizing long interconnects driven by the optimum Repeater system. Optimizing the line width to achieve the minimum power delay product, however, can satisfy current high speed, low-power design objectives. A reduction in power of 65% and delay of 97% is achieved for an example Repeater system.The Power-Delay-Area-Product (PDAP) criterion is introduced as an efficient technique to size the interconnect within a Repeater system. A reduction in buffer area of 67% and interconnect area of 46% is achieved based on the PDAP.
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Repeater insertion in tree structured inductive interconnect
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2001Co-Authors: Yehea Ismail, Eby G Friedman, Jose L. NevesAbstract:The effects of inductance on Repeater insertion in RLC trees is the focus of this paper. An algorithm is introduced to insert and size Repeaters within an RLC tree to optimize a variety of possible cost functions such as minimizing the maximum path delay, the skew between branches, or a combination of area, power, and delay. The algorithm has a complexity proportional to the square of the number of possible Repeater positions and determines a Repeater solution that is close to the global minimum. The Repeater insertion algorithm is used to insert Repeaters within several copper-based interconnect trees to minimize the maximum path delay based on both an RC model and an RLC model. The two buffering solutions are compared using the AS/X dynamic circuit simulator. It is shown that as inductance effects increase, the area and power consumed by the inserted Repeaters to minimize the path delays of an RLC tree decreases. By including inductance in the Repeater insertion methodology, the interconnect is modeled more accurately as compared to an RC model, permitting average savings in area, power, and delay of 40.8%, 15.6%, and 6.7%, respectively, for a variety of copper-based interconnect trees from a 0.25 /spl mu/m CMOS technology. The average savings in area, power, and delay increases to 62.2%, 57.2%, and 9.4%, respectively, when using five times faster devices with the same interconnect trees.
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Repeater Insertion in Tree Structured
2001Co-Authors: Yehea Ismail, Eby G Friedman, Jose L. NevesAbstract:The effects of inductance on Repeater insertion in trees is the focus of this paper. An algorithm is introduced to insert and size Repeaters within an tree to optimize a variety of possible cost functions such as minimizing the maximum path delay, the skew between branches, or a combination of area, power, and delay. The algorithm has a complexity proportional to the square of the number of possible Repeater positions and determines a Repeater solution that is close to the global minimum. The Repeater insertion algorithm is used to insert Repeaters within several copper-based interconnect trees to minimize the maximum path delay based on both an model and an model. The two buffering solutions are compared using the AS/X dynamic circuit simulator. It is shown that as inductance effects increase, the area and power consumed by the inserted Repeaters to min- imize the path delays of an tree decreases. By including inductance in the Repeater insertion methodology, the interconnect is modeled more accurately as compared to an model, permit- ting average savings in area, power, and delay of 40.8%, 15.6%, and 6.7%, respectively, for a variety of copper-based interconnect trees from a 0.25- m CMOS technology. The average savings in area, power, and delay increases to 62.2%, 57.2%, and 9.4%, respectively, when using five times faster devices with the same interconnect trees.
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Repeater design to reduce delay and power in resistive interconnect
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing, 1998Co-Authors: V Adler, Eby G FriedmanAbstract:In large chips, the propagation delay of the data and clock signals can limit performance due to long resistive interconnect. The insertion of Repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current, In order to develop a Repeater design methodology, a timing model characterizing a complementary metal-oxide-semiconductor (CMOS) inverter driving a resistance-capacitance (RC) load is presented. The model is based on the Sakurai short-channel /spl alpha/-power law model of transistor operation. The inverter model is applied to the problem of Repeaters to produce design expressions for determining the optimum number of uniformly sized Repeaters to be inserted along a resistive interconnect line for reduced delay. For a wide variety of typical RC loads, this analytical Repeater model exhibits a maximum error of 16% as compared to a dynamic circuit simulator (SPICE). The advantage of uniformly sized Repeaters versus tapered-buffer Repeaters is also investigated using the Repeater model presented in this paper. It is shown that uniform Repeaters remain advantageous over tapered buffers and tapered-buffer Repeaters even with relatively small resistive RC loads. An expression for the short-circuit power dissipation of a Repeater driving an RC load is presented, A comparison of the short-circuit power dissipation to the dynamic power dissipation in Repeater chains and related power/delay tradeoffs are made.
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Repeater design to reduce delay and power in resistive interconnect
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1998Co-Authors: V Adler, Eby G FriedmanAbstract:In large chips, the propagation delay of the data and clock signals can limit performance due to long resistive interconnect. The insertion of Repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current, In order to develop a Repeater design methodology, a timing model characterizing a complementary metal-oxide-semiconductor (CMOS) inverter driving a resistance-capacitance (RC) load is presented. The model is based on the Sakurai short-channel /spl alpha/-power law model of transistor operation. The inverter model is applied to the problem of Repeaters to produce design expressions for determining the optimum number of uniformly sized Repeaters to be inserted along a resistive interconnect line for reduced delay. For a wide variety of typical RC loads, this analytical Repeater model exhibits a maximum error of 16% as compared to a dynamic circuit simulator (SPICE). The advantage of uniformly sized Repeaters versus tapered-buffer Repeaters is also investigated using the Repeater model presented in this paper. It is shown that uniform Repeaters remain advantageous over tapered buffers and tapered-buffer Repeaters even with relatively small resistive RC loads. An expression for the short-circuit power dissipation of a Repeater driving an RC load is presented, A comparison of the short-circuit power dissipation to the dynamic power dissipation in Repeater chains and related power/delay tradeoffs are made.
Dukju Ahn - One of the best experts on this subject based on the ideXlab platform.
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A study on magnetic field Repeater in wireless power transfer
IEEE Transactions on Industrial Electronics, 2013Co-Authors: Dukju Ahn, Songcheol HongAbstract:It is shown that the distance of wireless power transfer is significantly increased by placing intermediate resonators (Repeaters) between transmitter and receiver. The guidelines are provided to use the Repeaters effectively. We first briefly review how the Repeaters enhance the transfer distance. Next, the aspect of resonant frequency splitting is studied separately both for even and odd numbers of Repeaters. The transferred power, efficiency, and output impedance phase are evaluated for each Repeater configuration. These provide the guidelines to select the optimum Repeater positions and numbers. We also propose and study a new kind of Repeater which can be placed (biased) even in the vicinity of transmitter or receiver. This increases the flexibility in choosing the Repeater position. The net effect of such biased Repeater is approximately doubling the effective coupling coefficient between transmitter and receiver. Experimental results are provided to prove the concepts.
Se-in Park - One of the best experts on this subject based on the ideXlab platform.
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APCC - The smart antenna module for RF Repeater
The 17th Asia Pacific Conference on Communications, 2011Co-Authors: Seong-goo Lee, Tae-seok Lee, Min-sang Kim, Dae-young Cho, Yong-hyun Seo, Kil-yung Kim, Dae-gun Cho, Se-in ParkAbstract:The signals received at the receiving antenna are consist of signals from base station (or mobile terminal) and transmitted signals from the other side of antenna in a RF Repeater. And the amplification rate of the RF Repeater is limited by the feedbacked signals from the same Repeater. Therefore, a receiving antenna has to be isolated from a transmitting antenna in order to reduce the effect of the feedbacked signal in the RF Repeater. Or, recently, ICS (interference cancellation system) techniques have been studied to estimate and to remove the feedback signals. However, it requires lots of hardware complexity and computational delay. To solve these problems, we have studied the implementation and adaptation of smart antenna system for RF Repeaters. We have designed a smart antenna module with switching beam structure in order to reduce the hardware and computational complexity. After analyzing the proposed smart antenna module, we found out that the proposed Repeater increases the amplification rate 15dB compare to the conventional RF Repeater.
