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Balasubramanian P - One of the best experts on this subject based on the ideXlab platform.
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Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder
2019Co-Authors: Balasubramanian P, Maskell D L, Mastorakis N EAbstract:We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead Adder with redundancy carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous Adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous Adders corresponding to various architectures such as ripple carry Adder (RCA), conventional carry lookahead Adder (CCLA), carry select Adder (CSLA), BCLARC, and hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimised. The cycle time (CT), which is the sum of forward and reverse latencies, governs the speed; and the product of average power dissipation and cycle time viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following average reductions in design metrics over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The Adders were implemented using a 32/28nm CMOS technology.Comment: PLOS ONE Preprint versio
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Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results
2019Co-Authors: Balasubramanian P, Maskell D L, Mastorakis N EAbstract:A new asynchronous early output block carry lookahead Adder (BCLA) incorporating redundant carries is proposed. Compared to the best of existing semi-custom asynchronous carry lookahead Adders (CLAs) employing delay-insensitive data encoding and following a 4-phase handshaking, the proposed BCLA with redundant carries achieves 13% reduction in forward latency and 14.8% reduction in cycle time compared to the best of the existing CLAs featuring redundant carries with no area or power penalty. A hybrid variant involving a ripple carry Adder (RCA) in the least significant stages i.e. BCLA-RCA is also considered that achieves a further 4% reduction in the forward latency and a 2.4% reduction in the cycle time compared to the proposed BCLA featuring redundant carries without area or power penalties
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Asynchronous Ripple Carry Adder based on Area Optimized Early Output Dual-Bit Full Adder
2018Co-Authors: Balasubramanian PAbstract:This technical note presents the design of a new area optimized asynchronous early output dual-bit full Adder (DBFA). An asynchronous ripple carry Adder (RCA) is constructed based on the new asynchronous DBFAs and existing asynchronous early output single-bit full Adders (SBFAs). The asynchronous DBFAs and SBFAs incorporate redundant logic and are encoded using the delay-insensitive dual-rail code (i.e. homogeneous data encoding) and follow a 4-phase return-to-zero handshaking. Compared to the previous asynchronous RCAs involving DBFAs and SBFAs, which are based on homogeneous or heterogeneous delay-insensitive data encodings and which correspond to different timing models, the early output asynchronous RCA incorporating the proposed DBFAs and/or SBFAs is found to result in reduced area for the dual-operand addition operation and feature significantly less latency than the asynchronous RCAs which consist of only SBFAs. The proposed asynchronous DBFA requires 28.6% less silicon than the previously reported asynchronous DBFA. For a 32-bit asynchronous RCA, utilizing 2 stages of SBFAs in the least significant positions and 15 stages of DBFAs in the more significant positions leads to optimization in the latency. The new early output 32-bit asynchronous RCA containing DBFAs and SBFAs reports the following optimizations in design metrics over its counterparts: i) 18.8% reduction in area than a previously reported 32-bit early output asynchronous RCA which also has 15 stages of DBFAs and 2 stages of SBFAs, ii) 29.4% reduction in latency than a 32-bit early output asynchronous RCA containing only SBFAs.Comment: 12 pages. arXiv admin note: substantial text overlap with arXiv:1706.04487, arXiv:1704.0761
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Performance Comparison of some Synchronous Adders
2018Co-Authors: Balasubramanian PAbstract:This technical note compares the performance of some synchronous Adders which correspond to the following architectures: i) ripple carry Adder (RCA), ii) recursive carry lookahead Adder (RCLA), iii) hybrid RCLA-RCA with the RCA used in the least significant Adder bit positions, iv) block carry lookahead Adder (BCLA), v) hybrid BCLA-RCA with the RCA used in the least significant Adder bit positions, and vi) non-uniform input partitioned carry select Adders (CSLAs) without and with the binary to excess-1 code (BEC) converter. The 32-bit addition was considered as an example operation. The Adder architectures mentioned were implemented by targeting a typical case PVT specification (high threshold voltage, supply voltage of 1.05V and operating temperature of 25 degrees Celsius) of the Synopsys 32/28nm CMOS technology. The comparison leads to the following observations: i) the hybrid CCLA-RCA is preferable to the other Adders in terms of the speed, the power-delay product, and the energy-delay product, ii) the non-uniform input partitioned CSLA without the BEC converter is preferable to the other Adders in terms of the area-delay product, and iii) the RCA incorporating the full Adder present in the standard digital cell library is preferable to the other Adders in terms of the power-delay-area product.Comment: 9 page
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Approximate Early Output Asynchronous Adders Based on Dual-Rail Data Encoding and 4-Phase Return-to-Zero and Return-to-One Handshaking
2018Co-Authors: Balasubramanian PAbstract:Approximate computing is emerging as an alternative to accurate computing due to its potential for realizing digital circuits and systems with low power dissipation, less critical path delay, and less area occupancy for an acceptable trade-off in the accuracy of results. In the domain of computer arithmetic, several approximate Adders and multipliers have been designed and their potential have been showcased versus accurate Adders and multipliers for practical digital signal processing applications. Nevertheless, in the existing literature, almost all the approximate Adders and multipliers reported correspond to the synchronous design method. In this work, we consider robust asynchronous i.e. quasi-delay-insensitive realizations of approximate Adders by employing delay-insensitive codes for data representation and processing, and the 4-phase handshake protocols for data communication. The 4-phase handshake protocols used are the return-to-zero and the return-to-one protocols. Specifically, we consider the implementations of 32-bit approximate Adders based on the return-to-zero and return-to-one handshake protocols by adopting the delay-insensitive dual-rail code for data encoding. We consider a range of approximations varying from 4-bits to 20-bits for the least significant positions of the accurate 32-bit asynchronous Adder. The asynchronous Adders correspond to early output (i.e. early reset) type, which are based on the well-known ripple carry Adder architecture. The experimental results show that approximate asynchronous Adders achieve reductions in the design metrics such as latency, cycle time, average power dissipation, and silicon area compared to the accurate asynchronous Adders. Further, the reductions in the design metrics are greater for the return-to-one protocol compared to the return-to-zero protocol. The design metrics were estimated using a 32/28nm CMOS technology.Comment: arXiv admin note: text overlap with arXiv:1711.0233
Mastorakis N E - One of the best experts on this subject based on the ideXlab platform.
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Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results
2019Co-Authors: Balasubramanian P, Maskell D L, Mastorakis N EAbstract:A new asynchronous early output block carry lookahead Adder (BCLA) incorporating redundant carries is proposed. Compared to the best of existing semi-custom asynchronous carry lookahead Adders (CLAs) employing delay-insensitive data encoding and following a 4-phase handshaking, the proposed BCLA with redundant carries achieves 13% reduction in forward latency and 14.8% reduction in cycle time compared to the best of the existing CLAs featuring redundant carries with no area or power penalty. A hybrid variant involving a ripple carry Adder (RCA) in the least significant stages i.e. BCLA-RCA is also considered that achieves a further 4% reduction in the forward latency and a 2.4% reduction in the cycle time compared to the proposed BCLA featuring redundant carries without area or power penalties
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Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder
2019Co-Authors: Balasubramanian P, Maskell D L, Mastorakis N EAbstract:We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead Adder with redundancy carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous Adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous Adders corresponding to various architectures such as ripple carry Adder (RCA), conventional carry lookahead Adder (CCLA), carry select Adder (CSLA), BCLARC, and hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimised. The cycle time (CT), which is the sum of forward and reverse latencies, governs the speed; and the product of average power dissipation and cycle time viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following average reductions in design metrics over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The Adders were implemented using a 32/28nm CMOS technology.Comment: PLOS ONE Preprint versio
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Speed and energy optimized quasi-delay-insensitive block carry lookahead Adder
'Public Library of Science (PLoS)', 2019Co-Authors: Mastorakis N E, Balasubramanian Padmanabhan, Maskell, Douglas LeslieAbstract:We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead Adder with redundant carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous Adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous Adders corresponding to various architectures such as the ripple carry Adder (RCA), the conventional carry lookahead Adder (CCLA), the carry select Adder (CSLA), the BCLARC, and the hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimized. The cycle time (CT), which is expressed as the sum of the worst-case times taken for processing the data and the spacer, governs the speed. The product of average power dissipation and CT viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following reductions in design metrics on average over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The Adders were implemented using a 32/28nm CMOS technology.MOE (Min. of Education, S’pore)Published versio
Duane S Boning - One of the best experts on this subject based on the ideXlab platform.
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an ultra compact virtual source fet model for deeply scaled devices parameter extraction and validation for standard cell libraries and digital circuits
Asia and South Pacific Design Automation Conference, 2013Co-Authors: O Mysore, Lan Wei, Luca Daniel, D A Antoniadis, Ibrahim M Elfadel, Duane S BoningAbstract:In this paper, we present the first validation of the virtual source (VS) charge-based compact model for standard cell libraries and large-scale digital circuits. With only a modest number of physically meaningful parameters, the VS model accounts for the main short-channel effects in nanometer technologies. Using a novel DC and transient parameter extraction methodology, the model is verified with simulated data from a well-characterized, industrial 40-nm bulk silicon model. The VS model is used to fully characterize a standard cell library with timing comparisons showing less than 2.7% error with respect to the industrial design kit. Furthermore, a 1001-stage inverter chain and a 32-bit Ripple-Carry Adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric Vdd sweeps show that the VS model is also ready for usage in low-power design methodologies. Finally, runtime comparisons have shown that the use of the VS model results in a speedup of about 7.6×.
Balasubramanian Padmanabhan - One of the best experts on this subject based on the ideXlab platform.
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Speed and energy optimized quasi-delay-insensitive block carry lookahead Adder
'Public Library of Science (PLoS)', 2019Co-Authors: Mastorakis N E, Balasubramanian Padmanabhan, Maskell, Douglas LeslieAbstract:We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead Adder with redundant carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous Adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous Adders corresponding to various architectures such as the ripple carry Adder (RCA), the conventional carry lookahead Adder (CCLA), the carry select Adder (CSLA), the BCLARC, and the hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimized. The cycle time (CT), which is expressed as the sum of the worst-case times taken for processing the data and the spacer, governs the speed. The product of average power dissipation and CT viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following reductions in design metrics on average over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The Adders were implemented using a 32/28nm CMOS technology.MOE (Min. of Education, S’pore)Published versio
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COMPARATIVE EVALUATION OF QUASI-DELAY-INSENSITIVE ASYNCHRONOUS AdderS CORRESPONDING TO RETURN-TO-ZERO AND RETURN-TO-ONE HANDSHAKING
Published by the University of Niš Serbia, 2017Co-Authors: Balasubramanian PadmanabhanAbstract:This article makes a comparative evaluation of quasi-delay-insensitive (QDI) asynchronous Adders, realized using the delay-insensitive dual-rail code, which adhere to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshake protocols. The QDI Adders realized correspond to the following Adder architectures: i) ripple carry Adder, ii) carry lookahead Adder, and iii) carry select Adder. The QDI Adders correspond to three different timing regimes viz. strong-indication, weak-indication and early output. They are physically implemented using a 32/28nm CMOS process. The comparative evaluation shows that, overall, QDI Adders which correspond to the 4-phase RTO handshake protocol are better than the QDI Adder counterparts which correspond to the 4-phase RTZ handshake protocol in terms of latency, area, and average power dissipation
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Approximate early output asynchronous Adders based on dual-rail data encoding and 4-phase return-to-zero and return-to-one handshaking
2017Co-Authors: Balasubramanian PadmanabhanAbstract:Approximate computing is emerging as an alternative to accurate computing due to its potential for realizing digital circuits and systems with low power dissipation, less critical path delay, and less area occupancy for an acceptable trade-off in the accuracy of results. In the domain of computer arithmetic, several approximate Adders and multipliers have been designed and their potential have been showcased versus accurate Adders and multipliers for practical digital signal processing applications. Nevertheless, in the existing literature, almost all the approximate Adders and multipliers reported correspond to the synchronous design method. In this work, we consider robust asynchronous i.e. quasi-delay-insensitive realizations of approximate Adders by employing delay-insensitive codes for data representation and processing, and the 4-phase handshake protocols for data communication. The 4-phase handshake protocols used are the return-to-zero and the return-to-one protocols. Specifically, we consider the implementations of 32-bit approximate Adders based on the return-to-zero and return-to-one handshake protocols by adopting the delay-insensitive dual-rail code for data encoding. We consider a range of approximations varying from 4-bits to 20-bits for the least significant positions of the accurate 32-bit asynchronous Adder. The asynchronous Adders correspond to early output (i.e. early reset) type, which are based on the well-known ripple carry Adder architecture. The experimental results show that approximate asynchronous Adders achieve reductions in the design metrics such as latency, cycle time, average power dissipation, and silicon area compared to the accurate asynchronous Adders. Further, the reductions in the design metrics are greater for the return-to-one protocol compared to the return-tozero protocol. The design metrics were estimated using a 32/28nm CMOS technology.Published versio
Prasad K - One of the best experts on this subject based on the ideXlab platform.
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Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding
2017Co-Authors: Balasubramanian P, Prasad KAbstract:Asynchronous circuits employing delay-insensitive codes for data representation i.e. encoding and following a 4-phase return-to-zero protocol for handshaking are generally robust. Depending upon whether a single delay-insensitive code or multiple delay-insensitive code(s) are used for data encoding, the encoding scheme is called homogeneous or heterogeneous delay-insensitive data encoding. This article proposes a new latency optimized early output asynchronous ripple carry Adder (RCA) that utilizes single-bit asynchronous full Adders (SAFAs) and dual-bit asynchronous full Adders (DAFAs) which incorporate redundant logic and are based on the delay-insensitive dual-rail code i.e. homogeneous data encoding, and follow a 4-phase return-to-zero handshaking. Amongst various RCA, carry lookahead Adder (CLA), and carry select Adder (CSLA) designs, which are based on homogeneous or heterogeneous delay-insensitive data encodings which correspond to the weak-indication or the early output timing model, the proposed early output asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is found to result in reduced latency for a dual-operand addition operation. In particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2 stages of SAFAs leads to reduced latency. The theoretical worst-case latencies of the different asynchronous Adders were calculated by taking into account the typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is made with their practical worst-case latencies estimated. The theoretical and practical worst-case latencies show a close correlation....Comment: arXiv admin note: text overlap with arXiv:1704.0761
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Latency Optimized Asynchronous Early Output Ripple Carry Adder Based on Delay-insensitive Dual-rail Data Encoding
'North Atlantic University Union (NAUN)', 2017Co-Authors: Balasubramanian P, Prasad KAbstract:Asynchronous circuits employing delay-insensitive codes for data representation i.e. encoding and following a 4-phase return-to-zero protocol for handshaking are generally robust. Depending upon whether a single delay-insensitive code or multiple delay-insensitive code(s) are used for data encoding, the encoding scheme is called homogeneous or heterogeneous delay-insensitive data encoding. This article proposes a new latency optimized early output asynchronous ripple carry Adder (RCA) that utilizes single-bit asynchronous full Adders (SAFAs) and dual-bit asynchronous full Adders (DAFAs) which incorporate redundant logic and are based on the delay-insensitive dual-rail code i.e. homogeneous data encoding, and follow a 4-phase return-to-zero handshaking. Amongst various RCA, carry lookahead Adder (CLA), and carry select Adder (CSLA) designs, which are based on homogeneous or heterogeneous delayinsensitive data encodings which correspond to the weak-indication or the early output timing model, the proposed early output asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is found to result in reduced latency for a dualoperand addition operation. In particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2 stages of SAFAs leads to reduced latency. The theoretical worst-case latencies of the different asynchronous Adders were calculated by taking into account the typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is made with their practical worst-case latencies estimated. The theoretical and practical worst-case latencies show a close correlation. The proposed early output 32-bit asynchronous RCA, which contains 2 stages of SAFAs in the least significant positions and 15 stages of DAFAs in the more significant positions, reports the following optimizations in latency over its architectural counterparts for a similar Adder size: i) 35.3% reduction in latency over a weakindication section-carry based CLA (SCBCLA), ii) 30.5% reduction in latency over a weak-indication hybrid SCBCLA-RCA, iii) 20.2% reduction in latency over an early output recursive CLA (RCLA), iv) 18.7% reduction in latency over an early output hybrid RCLA-RCA, and v) a 13% reduction in latency over an early output CSLA that features an optimum 8-8-8-8 uniform input partition
