The Experts below are selected from a list of 1074 Experts worldwide ranked by ideXlab platform
Jaydeep P Kulkarni - One of the best experts on this subject based on the ideXlab platform.
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ultralow voltage process variation tolerant Schmitt Trigger based sram design
IEEE Transactions on Very Large Scale Integration Systems, 2012Co-Authors: Jaydeep P Kulkarni, Kaushik RoyAbstract:We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read-stability as well as better write-ability compared to the standard 6T bitcell. The proposed ST bitcells incorporate a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes. A detailed comparison of different bitcells under iso-area condition shows that the ST-2 bitcell can operate at lower supply voltages. Measurement results on ten test-chips fabricated in 130-nm CMOS technology show that the proposed ST-2 bitcell gives 1.6× higher read static noise margin, 2× higher write-trip-point and 120-mV lower read-Vmin compared to the iso-area 6T bitcell.
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variation tolerant ultra low power heterojunction tunnel fet sram design
International Symposium on Nanoscale Architectures, 2011Co-Authors: Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, Jaydeep P KulkarniAbstract:Steep sub-threshold Interband Tunnel FETs (TFETs) are promising candidates for low supply voltage applications with higher switching performance than traditional CMOS. Unlike CMOS, TFETs exhibit uni-directional conduction due to their asymmetric source-drain architecture, and delayed output saturation characteristics. These unconventional characteristics of TFETs pose a challenge for providing good read/write noise margin characteristics in TFET SRAMs. We provide an analysis of 8T and 10T TFET SRAM cells, including Schmitt-Trigger (ST) based cells, to address these shortcomings. By benchmarking a variety of TFET-based SRAM cells, we show the utility of the Schmitt-Trigger feedback mechanism in improving the read/write noise margins, thus enabling ultra low-V CC operation for TFET SRAMs. We also propose a variation model for studying the impact of device-level variation on TFET SRAM cells. We show that the TFET ST SRAM cell has sufficient variation tolerance to operate at low-V CC , and is a very promising cell to achieve a V CC -min of 124mV. The TFET ST cell operating at its V CC -min provides a 1.2x reduction in dynamic energy and 13x reduction in leakage power compared to the best CMOS-based SRAM implementation operating at it's V CC -min, while giving better performance at the same time.
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process variation tolerant sram array for ultra low voltage applications
Design Automation Conference, 2008Co-Authors: Jaydeep P Kulkarni, Keejong Kim, Sang Phill Park, Kaushik RoyAbstract:In this work, we propose a Schmitt Trigger (ST) based differential sensing SRAM bitcell that can operate at ultra-low supply voltage. The proposed Schmitt Trigger SRAM cell addresses the fundamental conflicting design requirement of read versus write operation of a conventional 6T cell. Schmitt Trigger operation gives better read-stability and as well as better write- ability compared to the standard 6T cell. The proposed ST bitcell incorporates a built-in feedback mechanism, achieving process variation tolerance -- a must for future nano-scaled technology nodes. Measurements on 10 test-chips fabricated in 130 nm technology show that the proposed Schmitt Trigger bitcell gives 58% higher read Static Noise Margin (SNM), 2X higher write- trip-point and 120 mV lower read Vmin compared to the conventional 6T cell. The ST SRAM array is operational at 150mV of supply voltage.
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a 160 mv robust Schmitt Trigger based subthreshold sram
IEEE Journal of Solid-state Circuits, 2007Co-Authors: Jaydeep P KulkarniAbstract:We propose a novel Schmitt Trigger (ST) based differential 10-transistor SRAM (static random access memory) bitcell suitable for subthreshold operation. The proposed Schmitt Trigger based bitcell achieves 1.56 x higher read static noise margin (SNM) ( Vdd = 400 mV) compared to the conventional 6T cell. The robust Schmitt Trigger based memory cell exhibits built-in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes differential operation and hence does not require any architectural changes from the present 6T architecture. At iso-area and iso-read-failure probability the proposed memory bitcell operates at a lower (175 mV) Vdd with 18% reduction in leakage and 50% reduction in read/write power compared to the conventional 6T cell. Simulation results show that the proposed memory bitcell retains data at a supply voltage of 150 mV. Functional SRAM with the proposed memory bitcell is demonstrated at 160 mV in 0.13 mum CMOS technology.
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a 160 mv fully differential robust Schmitt Trigger based sub threshold sram
International Symposium on Low Power Electronics and Design, 2007Co-Authors: Jaydeep P Kulkarni, Keejong Kim, Kaushik RoyAbstract:We propose a novel Schmitt Trigger (ST) based fully differential 10 transistor SRAM (Static Random Access Memory) bitcell suitable for sub-threshold operation. The proposed Schmitt Trigger based bitcell achieves 1.56X higher read static noise margin (SNM) (VDD = 400mV) compared to the conventional 6T cell. The robust Schmitt Trigger based memory cell exhibits built in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes fully differential operation and hence does not require any architectural changes from the present 6T architecture. At iso-area and iso-read-failure probability the proposed memory bitcell operates at a lower (175mV) VDD with 18% reduction in leakage and 50% reduction in read/write power compared to the conventional 6T cell. Simulation results show that the proposed memory bitcell retains data at a supply voltage of 150mV. Functional SRAM with the proposed memory bitcell is demonstrated at 160mV in 0.13μm CMOS technology.
Chengta Chiang - One of the best experts on this subject based on the ideXlab platform.
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a low photocurrent cmos retinal focal plane sensor with a pseudo bjt smoothing network and an adaptive current Schmitt Trigger for scanner applications
IEEE Sensors Journal, 2004Co-Authors: Chengta ChiangAbstract:In this work, a new structure of low-photocurrent CMOS retinal focal-plane sensor with pseudo-BJT smoothing network and adaptive current Schmitt Trigger is proposed. The proposed structure is very simple and compact. This new circuit can easily be implemented in CMOS technology with a small chip area. Another innovation of this circuit is that the proposed circuit could be operated for low-induced current levels (pA), and the current hysteresis of the proposed current Schmitt Trigger could be adjusted adaptively according to the value of induced photocurrents. In this work, the detection of static and moving objects, such as a moving white bar, are proven by projecting a pattern through HSPICE simulation. The proposed retinal focal-plane sensor includes a 32 /spl times/ 32 pixel array with a pixel size of 70 /spl times/ 70 /spl mu/m/sup 2/. The fill factor is 75% and the total chip area is 3000 /spl times/ 3030 /spl mu/m/sup 2/. It is with fully functional 32 /spl times/ 32 implementations consuming less than 8.8 /spl mu/W per pixel at 3.3 V. Measurement results show that the proposed new retinal focal-plane sensor has successfully been used in character recognition of scanner systems, such as pen scanners, etc.
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a low photocurrent cmos retinal focal plane sensor with pseudo bjt smoothing network and adaptive current Schmitt Trigger for scanner applications
IEEE Sensors, 2003Co-Authors: Chengta ChiangAbstract:In this paper, a new structure of low-photocurrent CMOS retinal focal-plane sensor with pseudo-BJT smoothing network and adaptive current Schmitt Trigger is proposed. The proposed structure is very simple and compact. This new circuit can be easily implemented in CMOS technology with a small chip area. Besides, another innovation of this circuit is that the proposed circuit could be operated for low-induced current level (pA), and the current hysteresis of proposed current Schmitt Trigger could be adjusted adaptively according to the value of induced photocurrent. In this paper, the detection of static and moving objects, such as a moving white bar, are proven by projecting a pattern through HSPICE simulation. The proposed retinal focal-plane sensor includes 32 /spl times/ 32 pixel array with a pixel size of 70 /spl times/ 70 /spl mu/m/sup 2/. The fill factor is 75% and the total chip area is 3000 /spl times/ 3030 /spl mu/m/sup 2/. It is with fully functional 32 /spl times/ 32 implementations consuming less than 8.8 /spl mu/W per pixel at 3.3 V. Measurement results present the proposed retinal focal-plane sensor could be successfully used in character recognition, such as pen-scanner or etc.
Yiannos Manoli - One of the best experts on this subject based on the ideXlab platform.
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ultra sub threshold operation of always on digital circuits for iot applications by use of Schmitt Trigger gates
IEEE Transactions on Circuits and Systems I-regular Papers, 2017Co-Authors: Niklas Lotze, Yiannos ManoliAbstract:Supply-voltage reduction in digital circuits beyond the minimum energy per operation point is advantageous for supply-voltage-constrained applications and can help to considerably reduce standby power consumption. Schmitt Trigger (ST) logic allows for ultra-low voltage (ULV) operation; hardware implementations with supply voltages as low as 62mV have been demonstrated. In this paper, a systematic in-depth analysis of ST logic is presented. First, it is shown that ST logic allows for operation at supply voltages below the ultimate limit of standard digital CMOS circuits, making it—to the best of our knowledge—the only approach proposed to date for operation of digital circuits in this voltage region. The factors critical to the ultimate limit of supply voltage reduction are the ON-to-OFF current ratio of the transistors and the susceptibility to global variability. It is shown that ST logic provides improvements over standard CMOS logic in both of these aspects. The hysteresis that occurs in ST circuits at nominal supply voltage could potentially limit the applicability for ULV operation and is therefore carefully investigated. Furthermore, a systematic approach to optimum sizing of ST gates is presented for the first time. ST gates exhibit inherent overheads with respect to gate area, delay, and leakage, which are carefully evaluated. Compared with standard CMOS gates designed for the same minimum supply voltage, it is shown that ST gates, nevertheless, are the most efficient solution if the target minimum supply voltage is sufficiently low: with respect to area, this limit is at $V_{DD}\approx 110\,mV$ and with respect to power/delay at $V_{DD}\approx 75\,mV$ .
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fully integrated startup at 70 mv of boost converters for thermoelectric energy harvesting
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Jacob Goeppert, Yiannos ManoliAbstract:This paper presents an inductive DC-DC boost converter for energy harvesting using a thermoelectric generator with a minimum startup voltage of 70 mV and a regulated output voltage of 1.25 V. With a typical generator resistance of $40~\Omega $ , an output power of $17~ {\mu }\text{W}$ can be provided, which translates to an end-to-end efficiency of 58%. The converter employs Schmitt-Trigger logic startup control circuitry and an ultra-low voltage charge pump using modified Schmitt-Trigger driving circuits optimized for driving capacitive loads. Together with a novel ultra-low leakage power switch and the required control scheme, to the best of the authors’ knowledge, this enables the lowest minimum voltage with fully integrated startup.
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a 62 mv 0 13 mu m cmos standard cell based design technique using Schmitt Trigger logic
International Solid-State Circuits Conference, 2011Co-Authors: Niklas Lotze, Yiannos ManoliAbstract:Supply voltage reduction beyond the minimum energy per operation point is advantageous for supply voltage constrained applications, but is limited by the degradation of on-to-off current ratios with decreasing supply. In this work, we show that the effective on-to-off ratio can be considerably improved by the use of Schmitt Trigger structures, which effectively reduce the leakage from the gate output node and thereby stabilize the output level. A method for applying this concept to general logic is presented. Design rules concerning transistor sizing, gate selection and layout necessary to further minimize the required supply voltage are outlined and applied to the design of a chip implementing 8 × 8 bit multipliers as test structures. The only custom design step is the creation of the Schmitt Trigger standard-cell library, otherwise a regular digital tool chain is used. The multipliers exhibit full functionality down to supply voltages of 84 mV-62 mV, depending on the area overhead invested. No process or post-silicon tuning like body biasing is used. At the minimum possible supply voltage of 62 mV, a power consumption of 17.9 nW at an operation frequency of 5.2 kHz is measured for an 8 × 8 bit multiplier.
Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.
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ultralow voltage process variation tolerant Schmitt Trigger based sram design
IEEE Transactions on Very Large Scale Integration Systems, 2012Co-Authors: Jaydeep P Kulkarni, Kaushik RoyAbstract:We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read-stability as well as better write-ability compared to the standard 6T bitcell. The proposed ST bitcells incorporate a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes. A detailed comparison of different bitcells under iso-area condition shows that the ST-2 bitcell can operate at lower supply voltages. Measurement results on ten test-chips fabricated in 130-nm CMOS technology show that the proposed ST-2 bitcell gives 1.6× higher read static noise margin, 2× higher write-trip-point and 120-mV lower read-Vmin compared to the iso-area 6T bitcell.
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process variation tolerant sram array for ultra low voltage applications
Design Automation Conference, 2008Co-Authors: Jaydeep P Kulkarni, Keejong Kim, Sang Phill Park, Kaushik RoyAbstract:In this work, we propose a Schmitt Trigger (ST) based differential sensing SRAM bitcell that can operate at ultra-low supply voltage. The proposed Schmitt Trigger SRAM cell addresses the fundamental conflicting design requirement of read versus write operation of a conventional 6T cell. Schmitt Trigger operation gives better read-stability and as well as better write- ability compared to the standard 6T cell. The proposed ST bitcell incorporates a built-in feedback mechanism, achieving process variation tolerance -- a must for future nano-scaled technology nodes. Measurements on 10 test-chips fabricated in 130 nm technology show that the proposed Schmitt Trigger bitcell gives 58% higher read Static Noise Margin (SNM), 2X higher write- trip-point and 120 mV lower read Vmin compared to the conventional 6T cell. The ST SRAM array is operational at 150mV of supply voltage.
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a 160 mv fully differential robust Schmitt Trigger based sub threshold sram
International Symposium on Low Power Electronics and Design, 2007Co-Authors: Jaydeep P Kulkarni, Keejong Kim, Kaushik RoyAbstract:We propose a novel Schmitt Trigger (ST) based fully differential 10 transistor SRAM (Static Random Access Memory) bitcell suitable for sub-threshold operation. The proposed Schmitt Trigger based bitcell achieves 1.56X higher read static noise margin (SNM) (VDD = 400mV) compared to the conventional 6T cell. The robust Schmitt Trigger based memory cell exhibits built in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes fully differential operation and hence does not require any architectural changes from the present 6T architecture. At iso-area and iso-read-failure probability the proposed memory bitcell operates at a lower (175mV) VDD with 18% reduction in leakage and 50% reduction in read/write power compared to the conventional 6T cell. Simulation results show that the proposed memory bitcell retains data at a supply voltage of 150mV. Functional SRAM with the proposed memory bitcell is demonstrated at 160mV in 0.13μm CMOS technology.
Santosh Kumar Vishvakarma - One of the best experts on this subject based on the ideXlab platform.
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voltage bootstrapped Schmitt Trigger based radiation hardened latch design for reliable circuits
Great Lakes Symposium on VLSI, 2021Co-Authors: Neha Gupta, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Nikhil Agrawal, Narendra Singh Dhakad, P GirardAbstract:Soft error is one of the major reliability issue with technology scaling. In this work, we propose a radiation hardened voltage bootstrapped Schmitt Trigger (VB-ST) latch. To evaluate the circuit radiation resilience, we calculated the critical charge under the PVT variations at the most sensitive node and observed that the proposed latch has the highest critical charge and the lowest soft error rate ratio when compared to existing latches. We analyzed the impact of process variations on our design and observed that the VB-ST latch has 0.42x less critical voltage variability as compared to ST latch. Further, dynamic power and propagation delay are examined for various supply voltages, and we observed that the VB-ST latch has the lowest power consumption and delay propagation when compared to the other considered latches. For the validation of the proposed latch, a charge to power-delay-area product ratio (QPAR) is calculated and we clearly observed that the proposed VB-ST based latch significantly outperforms the performance of existing designs.
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Soft error hardened voltage bootstrapped Schmitt Trigger design for reliable circuits
Microelectronics Reliability, 2021Co-Authors: Neha Gupta, Ambika Prasad Shah, Narendra Singh Dhakad, Rana Sagar Kumar, Gopal Raut, Santosh Kumar VishvakarmaAbstract:Abstract Bias Temperature Instability and soft error rate are the major reliability issue with the technology scaling. BTI leads to an increase in the threshold voltage of the MOS transistors, which reduces the drain current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this paper, we propose a novel reliable voltage bootstrapped Schmitt Trigger circuit with soft error hardening enhancement and lower effect of BTI. We investigate all the circuit simulations which impact on the soft error rate of inverter circuits using HSPICE 65 nm CMOS technology. The results show that the proposed inverter circuit has a higher critical charge and lower soft error rate (SER) when compared to other reference inverter circuits. To better assess, we introduced Vth sensitivity and observed that the degradation of the proposed inverter circuit is 30% higher as compared to conventional CMOS inverter. The proposed inverter offers lower dynamic power, leakage power, and circuit delay of 91.11%, 93.47%, and 38.17%, respectively, as compared to CMOS inverter at 3 years of the stress time. Finally, the overall circuit performance is evaluated using the figure of merits and observes that the proposed inverter has the highest FOM correspond to other inverter circuits, which reveal that the proposed circuit is useful for the applications where the effect of radiations are higher.
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nbti stress delay sensitivity analysis of reliability enhanced Schmitt Trigger based circuits
Microelectronics Reliability, 2019Co-Authors: Ambika Prasad Shah, Santosh Kumar Vishvakarma, Sorin CotofanaAbstract:Abstract Negative Bias Temperature Instability (NBTI) in PMOS transistors results in increased transistor threshold voltage, is considered the major contributor to circuit performance degradation and to alleviate its effect appropriate design and lifetime measures are required. In this paper, we concentrate on a design-time solution, i.e., the replacement of CMOS inverters by more reliable counterparts, i.e., Schmitt Trigger (ST) and NMOS only Schmitt Trigger with Voltage Booster (NST-VB). We first compare the three candidates implemented in 32 nm CMOS technology concerning delay variation. Our results indicate that, after three years of NBTI stress, NST-VB exhibits an almost negligible delay shift of 0.47%, while ST and CMOS inverter experience a delay shift of 7.2% and 5.32%, respectively. Subsequently, we extend the scope and assume the ISCAS’89 s27 circuit as a discussion vehicle. Our evaluations indicate that after 3-year stress time, the critical path delay of the s27 CMOS, ST, and NST-VB based implementations increases by 105.1 ps, 185.2 ps, and 94.2 ps, respectively. To put things into a better perspective, we introduce the Inverse Power Area Reliability Product (IPARP) as compound reliability metric. Our analysis indicates that the normalized IPARP values for ST and NST-VB implementations are 0.062 and 1.903, respectively, compared to CMOS implementation.
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process variation and nbti resilient Schmitt Trigger for stable and reliable circuits
IEEE Transactions on Device and Materials Reliability, 2018Co-Authors: Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar, Santosh Kumar VishvakarmaAbstract:Negative bias temperature instability (NBTI) is a major time-dependent reliability concern with the pMOS transistor at elevated temperature. NBTI in pMOS is the severe dominating factor of circuit reliability as it increases the threshold voltage with time. In this paper, an nMOS-only Schmitt Trigger with a voltage booster (NST-VB) circuit is proposed. The use of only an nMOS transistor in the critical path of the Schmitt Trigger circuit drastically reduces the effect of NBTI on the circuit and, hence, improves performance. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of an nMOS-only structure. Because of NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% compared to 7.2% and 1.47% for the conventional Schmitt Trigger and nMOS inverter, respectively, after the stress time of three years. The proposed NST-VB circuit is also validated with an s27 benchmark circuit from the ISCAS’89 benchmark set and found that it has a lower effect of NBTI compared to CMOS and Schmitt Trigger inverter circuits. For the viability of the proposed circuit, figure-of-merit (FOM) is used as a performance metric and it is found that the proposed circuit has ${15.11\times }$ improved FOM compared to the conventional Schmitt Trigger circuit.
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nmos only Schmitt Trigger circuit for nbti resilient cmos circuits
Electronics Letters, 2018Co-Authors: Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar, Santosh Kumar VishvakarmaAbstract:A novel N-type MOS (NMOS) only Schmitt Trigger with voltage booster (NST-VB) circuit is presented. The proposed NST-VB circuit uses NMOS transistors in both pull-up and pull-down networks to reduce the effect of negative bias temperature instability (NBTI) on the circuit. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of NMOS only structure. Owing to NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% as compared with 7.2% for conventional Schmitt Trigger after the stress time of three years. For the viability of the proposed circuit figure of merit (FOM) is used as a performance metric and it is found that the proposed circuit has 15.35 × and 3.53 × improved FOM as compared with the conventional Schmitt Trigger and NMOS inverter, respectively.