The Experts below are selected from a list of 20817 Experts worldwide ranked by ideXlab platform
Jiting Liang - One of the best experts on this subject based on the ideXlab platform.
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reading operation and cell scalability of nonvolatile Schottky Barrier multibit charge trapping memory cells
IEEE Transactions on Electron Devices, 2012Co-Authors: Chunhsing Shih, Jiting Liang, Yanxiang LuoAbstract:Using unique ambipolar conduction, a Schottky Barrier multibit cell can be programmed using source-side electron injection and can be erased reversely using drain-side hole compensation. This paper numerically discusses the particular reading operation and cell scalability of the Schottky Barrier multibit cell resulting from the presence of Schottky source/drain Barriers. Forward and reverse reading schemes were examined to determine the multibit-cell state. Critical cell factors, such as channel length, Schottky Barrier height, and electrode voltage, were examined to select appropriate structural parameters and operational conditions. Because of the unique Schottky source/drain Barriers, the scaled Schottky Barrier cell exhibits excellent short-channel immunity and retains the nature of cell reading, source-side programming, and drain-side erasing in a nanoscale regime. Preserving a compact stack-gate architecture and a thorough CMOS process, the Schottky Barrier multibit cell serves as a promising candidate for use in nonvolatile embedded and commodity memory devices.
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nonvolatile Schottky Barrier multibit cell with source side injected programming and reverse drain side hole erasing
IEEE Transactions on Electron Devices, 2010Co-Authors: Chunhsing Shih, Jiting LiangAbstract:This paper presents a novel Schottky Barrier multibit cell with source-side injected programming and reverse drain-side hole erasing. Based on the unique ambipolar conduction of Schottky Barrier devices, the source Schottky Barrier promotes the amounts of hot electrons at a positive gate voltage to perform source-side injected programming, whereas the drain Schottky Barrier enhances the generations of hot holes at a negative gate voltage to carry out reverse drain-side erasing. The proposed Schottky Barrier charge-trapping cells are numerically demonstrated to exhibit low-voltage and high-efficiency programming/erasing without the presence of any gate versus source/drain bias tradeoff. The tight and matched distributions of injected carriers make this Schottky Barrier cell excellent in future multibit-cell applications.
D L Kwong - One of the best experts on this subject based on the ideXlab platform.
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improved carrier injection in gate all around Schottky Barrier silicon nanowire field effect transistors
Applied Physics Letters, 2008Co-Authors: Jianwei Peng, S J Lee, G Albert C Liang, N Singh, S Y Zhu, D L KwongAbstract:This letter presents the performance improvement of Schottky Barrier metal-oxide-semiconductor field-effect transistor by employing gate-all-around (GAA) Si-nanowire (SiNW) structure. Without employing any Barrier lowering technique, the mid-band-gap Ni-silicide Schottky Barrier transistors demonstrated excellent performance and achieved subthreshold slope of ∼86 mV/decade and on-current of 19 μA/μm on a 12.5 nm SiNW, and subthreshold slope of ∼79 mV/decade and on-current of 207 μA/μm on a 4 nm diameter SiNW. Assisted with simulation, we show that this improvement can be attributed to the strong reduction in the Schottky Barrier thickness as a result of the better gate control of GAA SiNW structure.
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germanium pmosfets with Schottky Barrier germanide s d high spl kappa gate dielectric and metal gate
IEEE Electron Device Letters, 2005Co-Authors: Shiyang Zhu, Janak Singh, Chunxiang Zhu, Albert Chin, Sungjoo Lee, D L KwongAbstract:Schottky-Barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as /spl sim/5 times due to the lower hole Schottky Barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.
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n type Schottky Barrier source drain mosfet using ytterbium silicide
IEEE Electron Device Letters, 2004Co-Authors: Shiyang Zhu, J D Chen, S J Lee, Janak Singh, Chunxiang Zhu, C H Tung, Albert Chin, D L KwongAbstract:Ytterbium silicide, for the first time, was used to form the Schottky Barrier source/drain (S/D) of N-channel MOSFETs. The device fabrication was performed at low temperature, which is highly preferred in the establishment of Schottky Barrier S/D transistor (SSDT) technology, including the HfO/sub 2/ gate dielectric, and HaN/TaN metal gate. The YbSi/sub 2 - x/ silicided N-SSDT has demonstrated a very promising characteristic with a recorded high I/sub on//l/sub off/ ratio of /spl sim/10/sup 7/ and a steep subthreshold slope of 75 mV/dec, which is attributed to the lower electron Barrier height and better film morphology of the YbSi/sub 2 - x//Si contact compared with other self-aligned rare earth metal-(Erbium, Terbium, Dysprosium) silicided Schottky junctions.
Chunhsing Shih - One of the best experts on this subject based on the ideXlab platform.
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reading operation and cell scalability of nonvolatile Schottky Barrier multibit charge trapping memory cells
IEEE Transactions on Electron Devices, 2012Co-Authors: Chunhsing Shih, Jiting Liang, Yanxiang LuoAbstract:Using unique ambipolar conduction, a Schottky Barrier multibit cell can be programmed using source-side electron injection and can be erased reversely using drain-side hole compensation. This paper numerically discusses the particular reading operation and cell scalability of the Schottky Barrier multibit cell resulting from the presence of Schottky source/drain Barriers. Forward and reverse reading schemes were examined to determine the multibit-cell state. Critical cell factors, such as channel length, Schottky Barrier height, and electrode voltage, were examined to select appropriate structural parameters and operational conditions. Because of the unique Schottky source/drain Barriers, the scaled Schottky Barrier cell exhibits excellent short-channel immunity and retains the nature of cell reading, source-side programming, and drain-side erasing in a nanoscale regime. Preserving a compact stack-gate architecture and a thorough CMOS process, the Schottky Barrier multibit cell serves as a promising candidate for use in nonvolatile embedded and commodity memory devices.
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nonvolatile Schottky Barrier multibit cell with source side injected programming and reverse drain side hole erasing
IEEE Transactions on Electron Devices, 2010Co-Authors: Chunhsing Shih, Jiting LiangAbstract:This paper presents a novel Schottky Barrier multibit cell with source-side injected programming and reverse drain-side hole erasing. Based on the unique ambipolar conduction of Schottky Barrier devices, the source Schottky Barrier promotes the amounts of hot electrons at a positive gate voltage to perform source-side injected programming, whereas the drain Schottky Barrier enhances the generations of hot holes at a negative gate voltage to carry out reverse drain-side erasing. The proposed Schottky Barrier charge-trapping cells are numerically demonstrated to exhibit low-voltage and high-efficiency programming/erasing without the presence of any gate versus source/drain bias tradeoff. The tight and matched distributions of injected carriers make this Schottky Barrier cell excellent in future multibit-cell applications.
Joerg Appenzeller - One of the best experts on this subject based on the ideXlab platform.
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bandgap extraction and device analysis of ionic liquid gated wse2 Schottky Barrier transistors
ACS Nano, 2017Co-Authors: Abhijith Prakash, Joerg AppenzellerAbstract:Through the careful study of ionic liquid gated WSe2 Schottky Barrier field-effect transistors as a function of flake thickness—referred to in the following as body thickness, tbody—critical insights into the electrical properties of WSe2 are gained. One finding is that the inverse subthreshold slope shows a clear dependence on body thickness, i.e., an approximate square root dependent increase with tbody, that provides evidence that injection into the WSe2 channel is mediated by thermally assisted tunneling through the gate-controlled Schottky Barriers at the source and drain. By employing our Schottky Barrier model, a detailed experimental plot of the WSe2 bandgap as a function of body thickness is obtained. We will discuss why the analysis employed here is critically dependent on the use of the above-mentioned ionic liquid gate and how device characteristics are analyzed in detail.
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analysing black phosphorus transistors using an analytic Schottky Barrier mosfet model
Nature Communications, 2015Co-Authors: Ashish V Penumatcha, R Salazar, Joerg AppenzellerAbstract:Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky Barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky Barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky Barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky Barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky Barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.
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physics of ultrathin body silicon on insulator Schottky Barrier field effect transistors
Applied Physics A, 2007Co-Authors: J Knoch, Joerg Appenzeller, M Zhang, S MantlAbstract:In this article we give an overview over the physical mechanisms involved in the electronic transport in ultrathin-body SOI Schottky-Barrier MOSFETs. A strong impact of the SOI and gate oxide thickness on the transistor characteristics is found and explained using experimental as well as simulated data. We elaborate on the influence of scattering in the channel and show that for a significant Barrier the on-state current is insensitive to scattering once the mean free path for scattering is larger than a characteristic length scale. In addition, recent efforts to lower the Schottky Barrier at the source/drain channel interfaces are presented. Using dopant segregation during silicidation significantly lower effective Schottky Barriers can be realized that allow for high performance SB-MOSFET devices.
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Carbon Nanotubes as Schottky Barrier Transistors
Physical Review Letters, 2002Co-Authors: Stefanie Heinze, Joerg Appenzeller, Vincent Derycke, Jerry Tersoff, Richard Martel, Phaedon AvourisAbstract:We show that carbon nanotube transistors operate as unconventional "Schottky Barrier transistors", in which transistor action occurs primarily by varying the contact resistance rather than the channel conductance. Transistor characteristics are calculated for both idealized and realistic geometries, and scaling behavior is demonstrated. Our results explain a variety of experimental observations, including the quite different effects of doping and adsorbed gases. The electrode geometry is shown to be crucial for good device performance.
Shiyang Zhu - One of the best experts on this subject based on the ideXlab platform.
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germanium pmosfets with Schottky Barrier germanide s d high spl kappa gate dielectric and metal gate
IEEE Electron Device Letters, 2005Co-Authors: Shiyang Zhu, Janak Singh, Chunxiang Zhu, Albert Chin, Sungjoo Lee, D L KwongAbstract:Schottky-Barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as /spl sim/5 times due to the lower hole Schottky Barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.
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n type Schottky Barrier source drain mosfet using ytterbium silicide
IEEE Electron Device Letters, 2004Co-Authors: Shiyang Zhu, J D Chen, S J Lee, Janak Singh, Chunxiang Zhu, C H Tung, Albert Chin, D L KwongAbstract:Ytterbium silicide, for the first time, was used to form the Schottky Barrier source/drain (S/D) of N-channel MOSFETs. The device fabrication was performed at low temperature, which is highly preferred in the establishment of Schottky Barrier S/D transistor (SSDT) technology, including the HfO/sub 2/ gate dielectric, and HaN/TaN metal gate. The YbSi/sub 2 - x/ silicided N-SSDT has demonstrated a very promising characteristic with a recorded high I/sub on//l/sub off/ ratio of /spl sim/10/sup 7/ and a steep subthreshold slope of 75 mV/dec, which is attributed to the lower electron Barrier height and better film morphology of the YbSi/sub 2 - x//Si contact compared with other self-aligned rare earth metal-(Erbium, Terbium, Dysprosium) silicided Schottky junctions.
