The Experts below are selected from a list of 1980 Experts worldwide ranked by ideXlab platform
Weisheng Zhao - One of the best experts on this subject based on the ideXlab platform.
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design and analysis of crossbar architecture based on complementary resistive switching non volatile memory cells
Journal of Parallel and Distributed Computing, 2014Co-Authors: Weisheng Zhao, Jacques-olivier Klein, J M Portal, Hassen Aziza, Yue Zhang, Wang Kang, Mathieu Moreau, Zhaohao Wang, Damien QuerliozAbstract:Abstract Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense research and development investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012), and could be used as both computing and storage memories beyond flash memories. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure enough current for the switching operation. This paper presents the design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells with a particular focus on reliability and power performance investigation. This architecture allows fewer Selection Transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture and provide fast data access for computing purpose. We perform transient and statistical simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 40 nm design kit and memory compact models, which were developed based on relative physics and experimental parameters.
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crossbar architecture based on 2r complementary resistive switching memory cell
International Symposium on Nanoscale Architectures, 2012Co-Authors: Weisheng Zhao, Jacques-olivier Klein, Claude Chappert, Dafine Ravelosona, Youguang Zhang, Damien Querlioz, Djaafar Chabi, J M Portal, Marc Bocquet, Hassen AzizaAbstract:Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012) beyond Flash memories. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure enough Current for the switching operation, This paper describes a design of crossbar architecture based on 2R complementary Resistive switching memory cell, This architecture allows fewer Selection Transistors, and minimum contacts between memory cells and CMOS control circuits, The complementary cell and parallel data sensing mitigate the impact of sneak Currents in the crossbar architecture, We performed transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 65 nm design kit and memory compact models.
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Crossbar architecture based on 2R complementary resistive switching memory cell
2012Co-Authors: Weisheng Zhao, Jacques-olivier Klein, Claude Chappert, Dafine Ravelosona, Youguang Zhang, Damien Querlioz, J M Portal, Marc Bocquet, Hassen Aziza, Damien DeleruyelleAbstract:Emerging non-volatile memoires (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >10 12) beyond Flash memories. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure enough current for the switching operation. This paper describes a design of crossbar architecture based on 2R complementary resistive switching memory cell. This architecture allows fewer Selection Transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture. We performed transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 65 nm design kit and memory compact models.
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Cross-point architecture for spin-transfer torque magnetic random access memory
IEEE Transactions on Nanotechnology, 2012Co-Authors: Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-olivier Klein, Claude Chappert, Pascale MazoyerAbstract:Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance, and nonvolatility. However, the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two Transistors, which are shared by a number of bits (e.g., 64). This leads to significant improvement of data density (e.g., 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low-speed issues of conventional cross-point architecture, which are difficult to surmount and few efficient design solutions have been reported in the literature. By using an STT-MRAM SPICE model including precise experimental parameters and STMicroelectronics 65 nm technology, some chip characteristic results such as cell area, data access speed, and power have been calculated or simulated to demonstrate the expected performances of this new memory architecture.
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High Density Spin-Transfer Torque (STT)-MRAM Based on Cross-Point Architecture
2012 4th IEEE International Memory Workshop, 2012Co-Authors: Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-olivier Klein, Claude Chappert, Dafine Ravelosona, Pascale MazoyerAbstract:Spin transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance and non-volatility. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two Transistors, which are shared by a number of bits (e.g. 64). This leads to significant improvement of data density (e.g. 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low speed issues of conventional cross-point architecture.
Sin-doo Lee - One of the best experts on this subject based on the ideXlab platform.
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Concept of rewritable organic ferroelectric random access memory in two lateral Transistors-in-one cell architecture
Semiconductor Science and Technology, 2014Co-Authors: Min-hoi Kim, Gyu Jeong Lee, Chang-min Keum, Sin-doo LeeAbstract:We propose a concept of rewritable ferroelectric random access memory (RAM) with two lateral organic Transistors-in-one cell architecture. Lateral integration of a paraelectric organic field-effect Transistor (OFET), being a Selection Transistor, and a ferroelectric OFET as a memory Transistor is realized using a paraelectric depolarizing layer (PDL) which is patterned on a ferroelectric insulator by transfer-printing. For the Selection Transistor, the key roles of the PDL are to reduce the dipolar strength and the surface roughness of the gate insulator, leading to the low memory on–off ratio and the high switching on–off current ratio. A new driving scheme preventing the crosstalk between adjacent memory cells is also demonstrated for the rewritable operation of the ferroelectric RAM.
Jacques-olivier Klein - One of the best experts on this subject based on the ideXlab platform.
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design and analysis of crossbar architecture based on complementary resistive switching non volatile memory cells
Journal of Parallel and Distributed Computing, 2014Co-Authors: Weisheng Zhao, Jacques-olivier Klein, J M Portal, Hassen Aziza, Yue Zhang, Wang Kang, Mathieu Moreau, Zhaohao Wang, Damien QuerliozAbstract:Abstract Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense research and development investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012), and could be used as both computing and storage memories beyond flash memories. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure enough current for the switching operation. This paper presents the design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells with a particular focus on reliability and power performance investigation. This architecture allows fewer Selection Transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture and provide fast data access for computing purpose. We perform transient and statistical simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 40 nm design kit and memory compact models, which were developed based on relative physics and experimental parameters.
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crossbar architecture based on 2r complementary resistive switching memory cell
International Symposium on Nanoscale Architectures, 2012Co-Authors: Weisheng Zhao, Jacques-olivier Klein, Claude Chappert, Dafine Ravelosona, Youguang Zhang, Damien Querlioz, Djaafar Chabi, J M Portal, Marc Bocquet, Hassen AzizaAbstract:Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012) beyond Flash memories. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure enough Current for the switching operation, This paper describes a design of crossbar architecture based on 2R complementary Resistive switching memory cell, This architecture allows fewer Selection Transistors, and minimum contacts between memory cells and CMOS control circuits, The complementary cell and parallel data sensing mitigate the impact of sneak Currents in the crossbar architecture, We performed transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 65 nm design kit and memory compact models.
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Crossbar architecture based on 2R complementary resistive switching memory cell
2012Co-Authors: Weisheng Zhao, Jacques-olivier Klein, Claude Chappert, Dafine Ravelosona, Youguang Zhang, Damien Querlioz, J M Portal, Marc Bocquet, Hassen Aziza, Damien DeleruyelleAbstract:Emerging non-volatile memoires (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >10 12) beyond Flash memories. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure enough current for the switching operation. This paper describes a design of crossbar architecture based on 2R complementary resistive switching memory cell. This architecture allows fewer Selection Transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture. We performed transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 65 nm design kit and memory compact models.
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Cross-point architecture for spin-transfer torque magnetic random access memory
IEEE Transactions on Nanotechnology, 2012Co-Authors: Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-olivier Klein, Claude Chappert, Pascale MazoyerAbstract:Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance, and nonvolatility. However, the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two Transistors, which are shared by a number of bits (e.g., 64). This leads to significant improvement of data density (e.g., 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low-speed issues of conventional cross-point architecture, which are difficult to surmount and few efficient design solutions have been reported in the literature. By using an STT-MRAM SPICE model including precise experimental parameters and STMicroelectronics 65 nm technology, some chip characteristic results such as cell area, data access speed, and power have been calculated or simulated to demonstrate the expected performances of this new memory architecture.
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High Density Spin-Transfer Torque (STT)-MRAM Based on Cross-Point Architecture
2012 4th IEEE International Memory Workshop, 2012Co-Authors: Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-olivier Klein, Claude Chappert, Dafine Ravelosona, Pascale MazoyerAbstract:Spin transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance and non-volatility. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two Transistors, which are shared by a number of bits (e.g. 64). This leads to significant improvement of data density (e.g. 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low speed issues of conventional cross-point architecture.
Naoki Kasai - One of the best experts on this subject based on the ideXlab platform.
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Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros
IEICE Transactions on Electronics, 2009Co-Authors: Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki KasaiAbstract:We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-Selection Transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology, which enables the same fast access time with a smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-µm CMOS process and a 0.24-µm MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64bits of data. The area size is reduced by more than 30%. By introducing a leakage-replication (LR) read scheme, a wide read margin on a test chip is accomplished and 50-ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.
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A 4-Mb MRAM macro comprising shared write-Selection Transistor cells and using a leakage-replication read scheme
2007 IEEE Asian Solid-State Circuits Conference, 2007Co-Authors: Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki KasaiAbstract:We propose an MRAM macro architecture for SoCs to reduce their area size. The .shared write-Selection Transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology', which enables the same fast access time as and with smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-mum CMOS process and a 0.24-mum MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64 hits of data. Area size is reduced by more than 30%. By introducing a leakage-replication (LR) read scheme, 50-ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.
Claude Chappert - One of the best experts on this subject based on the ideXlab platform.
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crossbar architecture based on 2r complementary resistive switching memory cell
International Symposium on Nanoscale Architectures, 2012Co-Authors: Weisheng Zhao, Jacques-olivier Klein, Claude Chappert, Dafine Ravelosona, Youguang Zhang, Damien Querlioz, Djaafar Chabi, J M Portal, Marc Bocquet, Hassen AzizaAbstract:Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012) beyond Flash memories. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure enough Current for the switching operation, This paper describes a design of crossbar architecture based on 2R complementary Resistive switching memory cell, This architecture allows fewer Selection Transistors, and minimum contacts between memory cells and CMOS control circuits, The complementary cell and parallel data sensing mitigate the impact of sneak Currents in the crossbar architecture, We performed transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 65 nm design kit and memory compact models.
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Crossbar architecture based on 2R complementary resistive switching memory cell
2012Co-Authors: Weisheng Zhao, Jacques-olivier Klein, Claude Chappert, Dafine Ravelosona, Youguang Zhang, Damien Querlioz, J M Portal, Marc Bocquet, Hassen Aziza, Damien DeleruyelleAbstract:Emerging non-volatile memoires (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >10 12) beyond Flash memories. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure enough current for the switching operation. This paper describes a design of crossbar architecture based on 2R complementary resistive switching memory cell. This architecture allows fewer Selection Transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture. We performed transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 65 nm design kit and memory compact models.
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Cross-point architecture for spin-transfer torque magnetic random access memory
IEEE Transactions on Nanotechnology, 2012Co-Authors: Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-olivier Klein, Claude Chappert, Pascale MazoyerAbstract:Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance, and nonvolatility. However, the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two Transistors, which are shared by a number of bits (e.g., 64). This leads to significant improvement of data density (e.g., 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low-speed issues of conventional cross-point architecture, which are difficult to surmount and few efficient design solutions have been reported in the literature. By using an STT-MRAM SPICE model including precise experimental parameters and STMicroelectronics 65 nm technology, some chip characteristic results such as cell area, data access speed, and power have been calculated or simulated to demonstrate the expected performances of this new memory architecture.
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High Density Spin-Transfer Torque (STT)-MRAM Based on Cross-Point Architecture
2012 4th IEEE International Memory Workshop, 2012Co-Authors: Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-olivier Klein, Claude Chappert, Dafine Ravelosona, Pascale MazoyerAbstract:Spin transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance and non-volatility. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two Transistors, which are shared by a number of bits (e.g. 64). This leads to significant improvement of data density (e.g. 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low speed issues of conventional cross-point architecture.
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NANOARCH - Crossbar architecture based on 2R complementary resistive switching memory cell
Proceedings of the 2012 IEEE ACM International Symposium on Nanoscale Architectures - NANOARCH '12, 2012Co-Authors: Weisheng Zhao, Jacques-olivier Klein, Claude Chappert, Dafine Ravelosona, Damien Querlioz, Djaafar Chabi, J M Portal, Marc Bocquet, Yue Zhang, Hassen AzizaAbstract:Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012) beyond Flash memories. However the conventional access architecture based on 1 Transistor + 1 memory cell limits its storage density as the Selection Transistor should be large enough to ensure enough Current for the switching operation, This paper describes a design of crossbar architecture based on 2R complementary Resistive switching memory cell, This architecture allows fewer Selection Transistors, and minimum contacts between memory cells and CMOS control circuits, The complementary cell and parallel data sensing mitigate the impact of sneak Currents in the crossbar architecture, We performed transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 65 nm design kit and memory compact models.