The Experts below are selected from a list of 10485 Experts worldwide ranked by ideXlab platform

Takashi Fukui - One of the best experts on this subject based on the ideXlab platform.

  • recent progress in integration of iii v nanowire transistors on si substrate by Selective Area Growth
    Journal of Physics D, 2014
    Co-Authors: Katsuhiro Tomioka, Takashi Fukui
    Abstract:

    We report on the recent progress in electronic applications using III–V nanowires (NWs) on Si substrates using the Selective-Area Growth method. This method could align vertical III–V NWs on Si under specific Growth conditions. Detailed studies of the III–V NW/Si heterointerface showed the possibility of achieving coherent Growth regardless of misfit dislocations in the III–V/Si heterojunction. The vertical III–V NWs grown using Selective-Area Growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III–V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III–V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.

  • Recent progress in integration of III?V nanowire transistors on Si substrate by Selective-Area Growth
    Journal of Physics D: Applied Physics, 2014
    Co-Authors: Katsuhiro Tomioka, Takashi Fukui
    Abstract:

    We report on the recent progress in electronic applications using III–V nanowires (NWs) on Si substrates using the Selective-Area Growth method. This method could align vertical III–V NWs on Si under specific Growth conditions. Detailed studies of the III–V NW/Si heterointerface showed the possibility of achieving coherent Growth regardless of misfit dislocations in the III–V/Si heterojunction. The vertical III–V NWs grown using Selective-Area Growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III–V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III–V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.

  • iii v nanowires on si substrate Selective Area Growth and device applications
    IEEE Journal of Selected Topics in Quantum Electronics, 2011
    Co-Authors: Katsuhiro Tomioka, Shinjiro Hara, Tomotaka Tanaka, Kenji Hiruma, Takashi Fukui
    Abstract:

    III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We present position-controlled and orientation-controlled Growth of InAs, GaAs, and InGaAs NWs on Si by Selective-Area Growth, and discuss how to control Growth directions of III-V NW on Si. Basic studies on III-V/Si interface showing heteroepitaxial Growth with misfit dislocations and coherent Growth without misfit dislocations are presented. Finally, we demonstrate the integrations of a III-V NW-based vertical surrounding-gate field-effect transistor and light-emitting diodes array on Si. These demonstrations could have broad applications in high-electron-mobility transistors, laser diodes, and photodiodes with a functionality not enabled by conventional NW devices.

  • III–V Nanowires on Si Substrate: Selective-Area Growth and Device Applications
    IEEE Journal of Selected Topics in Quantum Electronics, 2011
    Co-Authors: Katsuhiro Tomioka, Shinjiro Hara, Tomotaka Tanaka, Kenji Hiruma, Takashi Fukui
    Abstract:

    III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We present position-controlled and orientation-controlled Growth of InAs, GaAs, and InGaAs NWs on Si by Selective-Area Growth, and discuss how to control Growth directions of III-V NW on Si. Basic studies on III-V/Si interface showing heteroepitaxial Growth with misfit dislocations and coherent Growth without misfit dislocations are presented. Finally, we demonstrate the integrations of a III-V NW-based vertical surrounding-gate field-effect transistor and light-emitting diodes array on Si. These demonstrations could have broad applications in high-electron-mobility transistors, laser diodes, and photodiodes with a functionality not enabled by conventional NW devices.

Katsuhiro Tomioka - One of the best experts on this subject based on the ideXlab platform.

  • Composition controllability of InGaAs nanowire arrays in Selective Area Growth with controlled pitches on Si platform
    AIP Advances, 2017
    Co-Authors: Kohei Chiba, Katsuhiro Tomioka, Akinobu Yoshida, Junichi Motohisa
    Abstract:

    Composition controllability of vertical InGaAs nanowires (NWs) on Si integrated by Selective Area Growth was characterized for Si photonics in the optical telecommunication bands. The pitch of pre-patterned holes (NW sites) changed to an In/Ga alloy-composition in the solid phase during the NW Growth. The In composition with a nanometer-scaled pitch differed completely from that with a μm-scaled pitch. Accordingly, the Growth morphologies of InGaAs NWs show different behavior with respect to the In/Ga ratio.

  • recent progress in integration of iii v nanowire transistors on si substrate by Selective Area Growth
    Journal of Physics D, 2014
    Co-Authors: Katsuhiro Tomioka, Takashi Fukui
    Abstract:

    We report on the recent progress in electronic applications using III–V nanowires (NWs) on Si substrates using the Selective-Area Growth method. This method could align vertical III–V NWs on Si under specific Growth conditions. Detailed studies of the III–V NW/Si heterointerface showed the possibility of achieving coherent Growth regardless of misfit dislocations in the III–V/Si heterojunction. The vertical III–V NWs grown using Selective-Area Growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III–V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III–V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.

  • Recent progress in integration of III?V nanowire transistors on Si substrate by Selective-Area Growth
    Journal of Physics D: Applied Physics, 2014
    Co-Authors: Katsuhiro Tomioka, Takashi Fukui
    Abstract:

    We report on the recent progress in electronic applications using III–V nanowires (NWs) on Si substrates using the Selective-Area Growth method. This method could align vertical III–V NWs on Si under specific Growth conditions. Detailed studies of the III–V NW/Si heterointerface showed the possibility of achieving coherent Growth regardless of misfit dislocations in the III–V/Si heterojunction. The vertical III–V NWs grown using Selective-Area Growth were utilized for high performance vertical field-effect transistors (FETs). Furthermore, III–V NW/Si heterointerfaces with fewer misfit dislocations provided us with a unique band discontinuity with a new functionality that can be used for the application of tunnel diodes and tunnel FETs. These demonstrations could open the door to a new approach for creating low power switches using III–V NWs as building-blocks of future nanometre-scaled electronic circuits on Si platforms.

  • iii v nanowires on si substrate Selective Area Growth and device applications
    IEEE Journal of Selected Topics in Quantum Electronics, 2011
    Co-Authors: Katsuhiro Tomioka, Shinjiro Hara, Tomotaka Tanaka, Kenji Hiruma, Takashi Fukui
    Abstract:

    III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We present position-controlled and orientation-controlled Growth of InAs, GaAs, and InGaAs NWs on Si by Selective-Area Growth, and discuss how to control Growth directions of III-V NW on Si. Basic studies on III-V/Si interface showing heteroepitaxial Growth with misfit dislocations and coherent Growth without misfit dislocations are presented. Finally, we demonstrate the integrations of a III-V NW-based vertical surrounding-gate field-effect transistor and light-emitting diodes array on Si. These demonstrations could have broad applications in high-electron-mobility transistors, laser diodes, and photodiodes with a functionality not enabled by conventional NW devices.

  • III–V Nanowires on Si Substrate: Selective-Area Growth and Device Applications
    IEEE Journal of Selected Topics in Quantum Electronics, 2011
    Co-Authors: Katsuhiro Tomioka, Shinjiro Hara, Tomotaka Tanaka, Kenji Hiruma, Takashi Fukui
    Abstract:

    III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We present position-controlled and orientation-controlled Growth of InAs, GaAs, and InGaAs NWs on Si by Selective-Area Growth, and discuss how to control Growth directions of III-V NW on Si. Basic studies on III-V/Si interface showing heteroepitaxial Growth with misfit dislocations and coherent Growth without misfit dislocations are presented. Finally, we demonstrate the integrations of a III-V NW-based vertical surrounding-gate field-effect transistor and light-emitting diodes array on Si. These demonstrations could have broad applications in high-electron-mobility transistors, laser diodes, and photodiodes with a functionality not enabled by conventional NW devices.

Shinjiro Hara - One of the best experts on this subject based on the ideXlab platform.

  • Selective-Area Growth and transport properties of MnAs/InAs heterojunction nanowires
    Journal of Materials Research, 2019
    Co-Authors: Shinjiro Hara, Matthias T. Elm, Peter J. Klar
    Abstract:

    The authors summarize the results of Selective-Area Growth of vertical MnAs/InAs heterojunction nanowire (NW) arrays and present a preliminary characterization of the transport properties of a single MnAs/InAs heterojunction NW and a single InAs host NW for MnAs inclusions. During the endotaxy of MnAs after the Selective-Area Growth of host InAs nanowires (NWs) on partially SiO_2-masked GaAs(111)B substrates, hexagonal NiAs-type MnAs nanoclusters (NCs), which exhibit spontaneous magnetization at room temperature, are formed with the 〈0001〉 direction oriented parallel to the 〈111〉B direction of the zinc-blende-type InAs host NWs. For InAs host NWs, a large positive ordinary magnetoresistance (MR) effect up to 165% is observed at temperatures between 7 and 280 K. In addition, magnetotransport measurements reveal universal conductance fluctuations and a weak Anderson localization at temperatures up to 20 K due to a charge-accumulation layer formed at the surface. Single MnAs/InAs heterojunction NWs, however, exhibit only a negative MR effect, which is independent of temperature T < 10 K and linearly decreases up to −10% at 10 T with increasing magnetic field. These results reveal the tremendous influence of ferromagnetic NCs on the transport behavior inside the InAs host NWs.

  • iii v nanowires on si substrate Selective Area Growth and device applications
    IEEE Journal of Selected Topics in Quantum Electronics, 2011
    Co-Authors: Katsuhiro Tomioka, Shinjiro Hara, Tomotaka Tanaka, Kenji Hiruma, Takashi Fukui
    Abstract:

    III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We present position-controlled and orientation-controlled Growth of InAs, GaAs, and InGaAs NWs on Si by Selective-Area Growth, and discuss how to control Growth directions of III-V NW on Si. Basic studies on III-V/Si interface showing heteroepitaxial Growth with misfit dislocations and coherent Growth without misfit dislocations are presented. Finally, we demonstrate the integrations of a III-V NW-based vertical surrounding-gate field-effect transistor and light-emitting diodes array on Si. These demonstrations could have broad applications in high-electron-mobility transistors, laser diodes, and photodiodes with a functionality not enabled by conventional NW devices.

  • III–V Nanowires on Si Substrate: Selective-Area Growth and Device Applications
    IEEE Journal of Selected Topics in Quantum Electronics, 2011
    Co-Authors: Katsuhiro Tomioka, Shinjiro Hara, Tomotaka Tanaka, Kenji Hiruma, Takashi Fukui
    Abstract:

    III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We present position-controlled and orientation-controlled Growth of InAs, GaAs, and InGaAs NWs on Si by Selective-Area Growth, and discuss how to control Growth directions of III-V NW on Si. Basic studies on III-V/Si interface showing heteroepitaxial Growth with misfit dislocations and coherent Growth without misfit dislocations are presented. Finally, we demonstrate the integrations of a III-V NW-based vertical surrounding-gate field-effect transistor and light-emitting diodes array on Si. These demonstrations could have broad applications in high-electron-mobility transistors, laser diodes, and photodiodes with a functionality not enabled by conventional NW devices.

Gang Wang - One of the best experts on this subject based on the ideXlab platform.

  • Selective Area Growth of InP and Defect Elimination on Si (001) Substrates
    Journal of The Electrochemical Society, 2011
    Co-Authors: Gang Wang, Wei-e Wang, Niamh Waldron, Olivier Richard, Guy Brammertz, Maarten Leys, Hugo Bender, Johan Dekoster, Matty Caymax
    Abstract:

    We report the Selective Area Growth of InP layers in submicron trenches on Si (001) substrates by using a thin Ge buffer layer. The antiphase domain boundaries in InP layers are suppressed by engineering the local Ge surface profile. The mechanism of atomic step formation and the corresponding method for step density control are presented. We discuss the impact of the surface profile of the Ge buffer layer on the formation of antiphase domain boundaries as well as on InP nucleation. A minimum step density of 0.25 nm ―1 is required to avoid antiphase domain boundaries while a higher step density substantially reduces the stacking faults and twins in the InP nucleation layer. By employing the threading dislocation necking effect and the properly controlled Ge surface profile, high-quality InP layers have been obtained in submicron trenches.

  • enhancement mode algan gan heterostructure field effect transistors fabricated by Selective Area Growth technique
    Applied Physics Letters, 2011
    Co-Authors: Yuhua Wen, Gang Wang, Baijun Zhang, Ruihong Luo, Peng Xiang, Qingyu Deng, Zhen Shen, Hao Jiang, Yang Liu
    Abstract:

    In this letter, a method of using Selective Area Growth (SAG) technique was proposed to fabricate the enhancement-mode (E-mode) AlGaN/GaN heterostructure field effect transistors (HFETs), which can effectively avoid the plasma treatment damage to the active region of HFETs in comparison with the conventional methods. The SAG-HFETs exhibited a good performance of the maximum drain current of 300 mA/mm and peak transconductance of 135 mS/mm with a larger positive threshold voltage of 0.4 V. The results indicate that the SAG technique is a promising method to realize the high performance E-mode GaN based HFETs.

  • Selective Area Growth of high quality InP on Si (001) substrates
    Applied Physics Letters, 2010
    Co-Authors: Gang Wang, Wei-e Wang, Niamh Waldron, Olivier Richard, Guy Brammertz, Maarten Leys, Hugo Bender, Johan Dekoster, Roger Loo, Marc Seefeldt
    Abstract:

    In this work, we demonstrate the Selective Area Growth of high quality InP layers in submicron trenches on exactly (001) oriented Si substrates by using a thin Ge buffer layer. Antiphase domain boundaries were avoided by annealing at the Ge surface roughening temperature to create additional atomic steps on the Ge buffer layer. The mechanism of Ge surface atomic step formation and the corresponding step density control method are illustrated. The elimination of antiphase boundaries from the optimized Ge buffer layer, together with the defect necking effect, yield defect-free top InP layers inside the trenches.

Tomotaka Tanaka - One of the best experts on this subject based on the ideXlab platform.

  • iii v nanowires on si substrate Selective Area Growth and device applications
    IEEE Journal of Selected Topics in Quantum Electronics, 2011
    Co-Authors: Katsuhiro Tomioka, Shinjiro Hara, Tomotaka Tanaka, Kenji Hiruma, Takashi Fukui
    Abstract:

    III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We present position-controlled and orientation-controlled Growth of InAs, GaAs, and InGaAs NWs on Si by Selective-Area Growth, and discuss how to control Growth directions of III-V NW on Si. Basic studies on III-V/Si interface showing heteroepitaxial Growth with misfit dislocations and coherent Growth without misfit dislocations are presented. Finally, we demonstrate the integrations of a III-V NW-based vertical surrounding-gate field-effect transistor and light-emitting diodes array on Si. These demonstrations could have broad applications in high-electron-mobility transistors, laser diodes, and photodiodes with a functionality not enabled by conventional NW devices.

  • III–V Nanowires on Si Substrate: Selective-Area Growth and Device Applications
    IEEE Journal of Selected Topics in Quantum Electronics, 2011
    Co-Authors: Katsuhiro Tomioka, Shinjiro Hara, Tomotaka Tanaka, Kenji Hiruma, Takashi Fukui
    Abstract:

    III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We present position-controlled and orientation-controlled Growth of InAs, GaAs, and InGaAs NWs on Si by Selective-Area Growth, and discuss how to control Growth directions of III-V NW on Si. Basic studies on III-V/Si interface showing heteroepitaxial Growth with misfit dislocations and coherent Growth without misfit dislocations are presented. Finally, we demonstrate the integrations of a III-V NW-based vertical surrounding-gate field-effect transistor and light-emitting diodes array on Si. These demonstrations could have broad applications in high-electron-mobility transistors, laser diodes, and photodiodes with a functionality not enabled by conventional NW devices.