The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Paul R Berger - One of the best experts on this subject based on the ideXlab platform.
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high 5 2 peak to valley current ratio in si sige resonant interband Tunnel Diodes grown by chemical vapor deposition
Applied Physics Letters, 2012Co-Authors: Anisha Ramesh, Paul R Berger, Roger LooAbstract:Si/SiGe resonant interband Tunnel Diodes were fabricated using chemical vapor deposition (CVD) on 200-mm diameter p-doped silicon wafers. The resonant interband Tunnel diode structure consists of a p+-i-n+ diode that incorporates vapor phase doped δ-doping to enhance quantum mechanical Tunneling probability. The Tunneling barrier thickness is varied from 2 nm to 8 nm, and a record peak-to-valley current ratio of 5.2 for a CVD process is reported for a 6 nm barrier thickness with a room temperature peak Tunneling current of 20 A/cm2. The current density increases exponentially with spacer thickness reduction with a maximum value of 280 A/cm2 for a 2 nm barrier.
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si sige resonant interband Tunnel diode with f sub r0 20 2 ghz and peak current density 218 ka cm sup 2 for k band mixed signal applications
IEEE Electron Device Letters, 2006Co-Authors: Sungyong Chung, Paul R Berger, Ronghua Yu, Siyoung Park, P E ThompsonAbstract:This letter presents the room-temperature high-frequency operation of Si/SiGe-based resonant interband Tunnel Diodes that were fabricated by low-temperature molecular beam epitaxy. The resulting devices show a resistive cutoff frequency f/sub r0/ of 20.2 GHz with a peak current density of 218 kA/cm/sup 2/, a speed index of 35.9 mV/ps, and a peak-to-valley current ratio of 1.47. A specific contact resistivity of 5.3/spl times/10/sup -7/ /spl Omega//spl middot/cm/sup 2/ extracted from RF measurements was achieved by Ni silicidation through a P /spl delta/-doped quantum well by rapid thermal sintering at 430/spl deg/C for 30 s. The resulting devices are very good candidates for RF high-power mixed-signal applications. The device structures presented here are compatible with a standard complementary metal-oxide-semiconductor or heterojunction bipolar transistor process.
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room temperature negative differential resistance in polymer Tunnel Diodes using a thin oxide layer and demonstration of threshold logic
Applied Physics Letters, 2005Co-Authors: Woojun Yoon, Paul R Berger, Sungyong Chung, Sita M AsarAbstract:Conjugated polymers, with π molecular orbitals delocalized along the polymer chain, are useful organic semiconductors that provide the possibility of molecular electronics for low-power organic-based memory and logic. Quantum functional devices based upon carrier Tunneling processes open vistas into very efficient and low-power consumption circuitry that would be ideal for these applications. We demonstrate here strong room temperature negative differential resistance (NDR) for poly[2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylenevinylene] (MEH-PPV) polymer Tunnel Diodes (PTD) using a thin TiO2 Tunneling layer (∼2–8nm) sandwiched between the MEH-PPV and the indium tin oxide anode. A key advantage is the pronounced NDR using a thick polymer layer with a large active area, circumnavigating the need for molecularly-sized junctions. Current-voltage measurements show large and reproducible NDR with a PVCR as high as 53 at room temperature. We also demonstrate basic logic circuit operation using a pair of these PT...
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three terminal si based negative differential resistance circuit element with adjustable peak to valley current ratios using a monolithic vertical integration
Applied Physics Letters, 2004Co-Authors: Sungyong Chung, Phillip E Thompson, S L Rommel, Roger K Lake, Paul R Berger, Niu Jin, S K KurinecAbstract:Si-based resonant bipolar transistors are demonstrated by the monolithic vertical integration of Si-based resonant interband Tunnel Diodes atop the emitter of Si/SiGe heterojunction bipolar transistors (HBTs) on a silicon substrate. In the common emitter configuration, IC versus VCE shows negative differential resistance characteristics. The resulting characteristics are adjustable peak-to-valley current ratios, including infinite and negative values, and tailorable peak current densities by the control of the HBT base current under room temperature operation. With the integrated RITD-HBT combination, latching properties which are the key operating principle for high-speed mixed-signal, memory, and logic circuitry, are experimentally demonstrated.
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three terminal si based negative differential resistance circuit element with adjustable peak to valley current ratios using a monolithic vertical integration
Journal of Applied Physics, 2004Co-Authors: Sungyong Chung, Phillip E Thompson, S L Rommel, Roger K Lake, Paul R Berger, Niu Jin, S K KurinecAbstract:Si-based resonant bipolar transistors are demonstrated by the monolithic vertical integration of Si-based resonant interband Tunnel Diodes atop the emitter of Si/SiGe heterojunction bipolar transistors ~HBTs! on a silicon substrate. In the common emitter configuration, IC versus VCE shows negative differential resistance characteristics. The resulting characteristics are adjustable peak-to-valley current ratios, including infinite and negative values, and tailorable peak current densities by the control of the HBT base current under room temperature operation. With the integrated RITD-HBT combination, latching properties which are the key operating principle for high-speed mixed-signal, memory, and logic circuitry, are experimentally demonstrated. © 2004 American Institute of Physics. @DOI: 10.1063/1.1690109#
Sungyong Chung - One of the best experts on this subject based on the ideXlab platform.
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si sige resonant interband Tunnel diode with f sub r0 20 2 ghz and peak current density 218 ka cm sup 2 for k band mixed signal applications
IEEE Electron Device Letters, 2006Co-Authors: Sungyong Chung, Paul R Berger, Ronghua Yu, Siyoung Park, P E ThompsonAbstract:This letter presents the room-temperature high-frequency operation of Si/SiGe-based resonant interband Tunnel Diodes that were fabricated by low-temperature molecular beam epitaxy. The resulting devices show a resistive cutoff frequency f/sub r0/ of 20.2 GHz with a peak current density of 218 kA/cm/sup 2/, a speed index of 35.9 mV/ps, and a peak-to-valley current ratio of 1.47. A specific contact resistivity of 5.3/spl times/10/sup -7/ /spl Omega//spl middot/cm/sup 2/ extracted from RF measurements was achieved by Ni silicidation through a P /spl delta/-doped quantum well by rapid thermal sintering at 430/spl deg/C for 30 s. The resulting devices are very good candidates for RF high-power mixed-signal applications. The device structures presented here are compatible with a standard complementary metal-oxide-semiconductor or heterojunction bipolar transistor process.
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room temperature negative differential resistance in polymer Tunnel Diodes using a thin oxide layer and demonstration of threshold logic
Applied Physics Letters, 2005Co-Authors: Woojun Yoon, Paul R Berger, Sungyong Chung, Sita M AsarAbstract:Conjugated polymers, with π molecular orbitals delocalized along the polymer chain, are useful organic semiconductors that provide the possibility of molecular electronics for low-power organic-based memory and logic. Quantum functional devices based upon carrier Tunneling processes open vistas into very efficient and low-power consumption circuitry that would be ideal for these applications. We demonstrate here strong room temperature negative differential resistance (NDR) for poly[2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylenevinylene] (MEH-PPV) polymer Tunnel Diodes (PTD) using a thin TiO2 Tunneling layer (∼2–8nm) sandwiched between the MEH-PPV and the indium tin oxide anode. A key advantage is the pronounced NDR using a thick polymer layer with a large active area, circumnavigating the need for molecularly-sized junctions. Current-voltage measurements show large and reproducible NDR with a PVCR as high as 53 at room temperature. We also demonstrate basic logic circuit operation using a pair of these PT...
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three terminal si based negative differential resistance circuit element with adjustable peak to valley current ratios using a monolithic vertical integration
Applied Physics Letters, 2004Co-Authors: Sungyong Chung, Phillip E Thompson, S L Rommel, Roger K Lake, Paul R Berger, Niu Jin, S K KurinecAbstract:Si-based resonant bipolar transistors are demonstrated by the monolithic vertical integration of Si-based resonant interband Tunnel Diodes atop the emitter of Si/SiGe heterojunction bipolar transistors (HBTs) on a silicon substrate. In the common emitter configuration, IC versus VCE shows negative differential resistance characteristics. The resulting characteristics are adjustable peak-to-valley current ratios, including infinite and negative values, and tailorable peak current densities by the control of the HBT base current under room temperature operation. With the integrated RITD-HBT combination, latching properties which are the key operating principle for high-speed mixed-signal, memory, and logic circuitry, are experimentally demonstrated.
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three terminal si based negative differential resistance circuit element with adjustable peak to valley current ratios using a monolithic vertical integration
Journal of Applied Physics, 2004Co-Authors: Sungyong Chung, Phillip E Thompson, S L Rommel, Roger K Lake, Paul R Berger, Niu Jin, S K KurinecAbstract:Si-based resonant bipolar transistors are demonstrated by the monolithic vertical integration of Si-based resonant interband Tunnel Diodes atop the emitter of Si/SiGe heterojunction bipolar transistors ~HBTs! on a silicon substrate. In the common emitter configuration, IC versus VCE shows negative differential resistance characteristics. The resulting characteristics are adjustable peak-to-valley current ratios, including infinite and negative values, and tailorable peak current densities by the control of the HBT base current under room temperature operation. With the integrated RITD-HBT combination, latching properties which are the key operating principle for high-speed mixed-signal, memory, and logic circuitry, are experimentally demonstrated. © 2004 American Institute of Physics. @DOI: 10.1063/1.1690109#
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diffusion barrier cladding in si sige resonant interband Tunneling Diodes and their patterned growth on pmos source drain regions
IEEE Transactions on Electron Devices, 2003Co-Authors: Niu Jin, Phillip E Thompson, S Sudirgo, Roger K Lake, Paul R Berger, Sungyong Chung, A T Rice, C Rivas, J J Kempisty, B CuranovicAbstract:Si/SiGe resonant interband Tunnel Diodes (RITDs) employing /spl delta/-doping spikes that demonstrate negative differential resistance (NDR) at room temperature are presented. Efforts have focused on improving the Tunnel diode peak-to-valley current ratio (PVCR) figure-of-merit, as well as addressing issues of manufacturability and CMOS integration. Thin SiGe layers sandwiching the B /spl delta/-doping spike used to suppress B out-diffusion are discussed. A room-temperature PVCR of 3.6 was measured with a peak current density of 0.3 kA/cm/sup 2/. Results clearly show that by introducing SiGe layers to clad the B /spl delta/-doping layer, B diffusion is suppressed during post-growth annealing, which raises the thermal budget. A higher RTA temperature appears to be more effective in reducing defects and results in a lower valley current and higher PVCR. RITDs grown by selective area molecular beam epitaxy (MBE) have been realized inside of low-temperature oxide openings, with performance comparable with RITDs grown on bulk substrates.
S L Rommel - One of the best experts on this subject based on the ideXlab platform.
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benchmarking current density in staggered gap in0 53ga0 47as gaas0 5sb0 5 heterojunction esaki Tunnel Diodes
Applied Physics Letters, 2013Co-Authors: Brian Romanczyk, S L Rommel, Paul Thomas, D Pawlik, W Y Loh, Man Hoi Wong, Kausik Majumdar, W E Wang, P D KirschAbstract:The impact of dopant concentration on the current densities of In0.53Ga0.47As/GaAs0.5Sb0.5 heterojunction Esaki Tunnel Diodes is investigated. Increased doping density results in increased peak and Zener current densities. Two different structures were fabricated demonstrating peak current densities of 92 kA/cm2 and 572 kA/cm2, Zener current densities of 994 kA/cm2 and 5.1 MA/cm2 at a −0.5 V bias, and peak-to-valley current ratios of 6.0 and 5.4, respectively. The peak current scaled linearly with area down to a 70 nm diameter. The peak current densities were benchmarked against Esaki Diodes from other material systems based on doping density and Tunnel barrier height.
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record pvcr gaas based Tunnel Diodes fabricated on si substrates using aspect ratio trapping
International Electron Devices Meeting, 2008Co-Authors: S L Rommel, S K Kurinec, Alan Seabaugh, Paul Thomas, D Pawlik, M Barth, K Johnson, Z Cheng, Jisoo Park, J M HydrickAbstract:High quality, low defect GaAs virtual substrates on Si, produced by the aspect ratio trapping growth technique, have been used for the fabrication of n+GaAs/n+InGaAs/p+GaAs Esaki Diodes. All epitaxial layers were grown by reduced-pressure chemical vapor deposition/metalorganic chemical vapor deposition , instead of the molecular beam epitaxy technique commonly used for most high performance Esaki Diodes. Four Esaki diode structures were fabricated and measured, with current densities up to 1 kA/cm2. Peak-to-valley current ratios up to 56 have been achieved, which is greater than twice that of the best GaAs Esaki Diodes previously reported.
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monolithically integrated si sige resonant interband Tunnel diode cmos demonstrating low voltage mobile operation
Solid-state Electronics, 2004Co-Authors: S Sudirgo, S L Rommel, R P Nandgaonkar, B Curanovic, J Hebding, R Saxer, Syed S Islam, K D Hirschman, S K Kurinec, Phillip E ThompsonAbstract:The first demonstration of the monolithic integration of CMOS and Si/SiGe resonant interband Tunnel Diodes (RITD) with negative differential resistance (NDR) is reported in this paper. The Si/SiGe RITDs exhibited a peak-tovalley current ratio (PVCR) up to 2.8 and peak current density (Jp) of 0.26 kA/cm 2 at room temperature. This study focused on the utilization of a pair of Tunnel Diodes connected in series to form a latch. Employing a FET to supply current into the latch, a RITD/NMOS monostable–bistable transition logic element (MOBILE) was realized. The latch exhibited a voltage swing of 84% at an applied supply voltage of 0.5 V. This logic element enables low voltage operation for high density circuit design of embedded memory.
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three terminal si based negative differential resistance circuit element with adjustable peak to valley current ratios using a monolithic vertical integration
Applied Physics Letters, 2004Co-Authors: Sungyong Chung, Phillip E Thompson, S L Rommel, Roger K Lake, Paul R Berger, Niu Jin, S K KurinecAbstract:Si-based resonant bipolar transistors are demonstrated by the monolithic vertical integration of Si-based resonant interband Tunnel Diodes atop the emitter of Si/SiGe heterojunction bipolar transistors (HBTs) on a silicon substrate. In the common emitter configuration, IC versus VCE shows negative differential resistance characteristics. The resulting characteristics are adjustable peak-to-valley current ratios, including infinite and negative values, and tailorable peak current densities by the control of the HBT base current under room temperature operation. With the integrated RITD-HBT combination, latching properties which are the key operating principle for high-speed mixed-signal, memory, and logic circuitry, are experimentally demonstrated.
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three terminal si based negative differential resistance circuit element with adjustable peak to valley current ratios using a monolithic vertical integration
Journal of Applied Physics, 2004Co-Authors: Sungyong Chung, Phillip E Thompson, S L Rommel, Roger K Lake, Paul R Berger, Niu Jin, S K KurinecAbstract:Si-based resonant bipolar transistors are demonstrated by the monolithic vertical integration of Si-based resonant interband Tunnel Diodes atop the emitter of Si/SiGe heterojunction bipolar transistors ~HBTs! on a silicon substrate. In the common emitter configuration, IC versus VCE shows negative differential resistance characteristics. The resulting characteristics are adjustable peak-to-valley current ratios, including infinite and negative values, and tailorable peak current densities by the control of the HBT base current under room temperature operation. With the integrated RITD-HBT combination, latching properties which are the key operating principle for high-speed mixed-signal, memory, and logic circuitry, are experimentally demonstrated. © 2004 American Institute of Physics. @DOI: 10.1063/1.1690109#
Heike Riel - One of the best experts on this subject based on the ideXlab platform.
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Vertical III-V nanowire device integration on Si(100)
Nano Letters, 2014Co-Authors: Mattias Borg, Chris Breslin, Pratyush Das Kanungo, Heinz Schmid, L Gignac, Kirsten E. Moselund, John Bruley, Peter Werner, Giorgio Signorello, Heike RielAbstract:We report complementary metal-oxide-semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire Tunnel Diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.
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inas si heterojunction nanowire Tunnel Diodes and Tunnel fets
International Electron Devices Meeting, 2012Co-Authors: Heike Riel, Kirsten E. Moselund, Cedric D Bessire, Mikael Bjork, Andreas Schenk, H Ghoneim, Heinz SchmidAbstract:In this paper we present vertical Tunnel Diodes and Tunnel FETs (TFETs) based on III-V-Si nanowire heterojunctions. We experimentally demonstrate InAs-Si Esaki Tunnel Diodes with record high currents of 6 MA/cm2 at 0.5 V in reverse bias. Furthermore, we have fabricated vertical InAs-Si nanowire TFETs with gate-all-around architecture and high-k dielectrics. The InAs-Si combination allows achieving high I on /I off ratios above 106, with I on of 2.4 μA/μm and an inverse subthreshold slope of 150 mV/dec over three decades. The achieved improvements can be attributed to increased nanowire doping and Ni alloying of the top contact. The results indicate the benefits of the InAs-Si material system combining the possibility of achieving high I on with high I on /I off ratio.
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trap assisted Tunneling in si inas nanowire heterojunction Tunnel Diodes
Nano Letters, 2011Co-Authors: Cedric D Bessire, Heinz Schmid, Andreas Schenk, M T Bjork, Kathleen B Reuter, Heike RielAbstract:We report on the electrical characterization of one-sided p(+)-si/n-InAs nanowire heterojunction Tunnel Diodes to provide insight into the Tunnel process occurring in this highly lattice mismatched material system. The lattice mismatch gives rise to dislocations at the interface as confirmed by electron microscopy. Despite this, a negative differential resistance with peak-to-valley current ratios of up to 2.4 at room temperature and with large current densities is observed, attesting to the very abrupt and high-quality interface. The presence of dislocations and other defects that increase the excess current is evident in the first and second derivative of the I-V characteristics as distinct peaks arising from trap-and phonon-assisted Tunneling via the corresponding defect levels. We observe this assisted Tunneling mainly in the forward direction and at low reverse bias but not at higher reverse biases because the band-to-band generation rates are peaked in the InAs, which is also confirmed by modeling. This indicates that most of the peaks are due to dislocations and defects in the immediate vicinity of the interface. Finally, we also demonstrate that these devices are very sensitive to electrical stress, in particular at room temperature, because of the extremely high electrical fields obtained at the abrupt junction even at low bias. The electrical stress induces additional defect levels in the band gap, which reduce the peak-to-valley current ratios.
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si inas heterojunction esaki Tunnel Diodes with high current densities
Applied Physics Letters, 2010Co-Authors: M T Bjork, Heinz Schmid, Kirsten E. Moselund, Cedric D Bessire, H Ghoneim, S Karg, Emanuel Lortscher, Heike RielAbstract:Si–InAs heterojunction p-n Diodes were fabricated by growing InAs nanowires in oxide mask openings on silicon substrates. At substrate doping concentrations of 1×1016 and 1×1019 cm−3, conventional diode characteristics were obtained, from which a valence band offset between Si and InAs of 130 meV was extracted. For a substrate doping of 4×1019 cm−3, heterojunction Tunnel diode characteristics were obtained showing current densities in the range of 50 kA/cm2 at 0.5 V reverse bias. In addition, in situ doping of the InAs wires was performed using disilane to further boost the Tunnel currents up to 100 kA/cm2 at 0.5 V reverse bias for the highest doping ratios.
S K Kurinec - One of the best experts on this subject based on the ideXlab platform.
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record pvcr gaas based Tunnel Diodes fabricated on si substrates using aspect ratio trapping
International Electron Devices Meeting, 2008Co-Authors: S L Rommel, S K Kurinec, Alan Seabaugh, Paul Thomas, D Pawlik, M Barth, K Johnson, Z Cheng, Jisoo Park, J M HydrickAbstract:High quality, low defect GaAs virtual substrates on Si, produced by the aspect ratio trapping growth technique, have been used for the fabrication of n+GaAs/n+InGaAs/p+GaAs Esaki Diodes. All epitaxial layers were grown by reduced-pressure chemical vapor deposition/metalorganic chemical vapor deposition , instead of the molecular beam epitaxy technique commonly used for most high performance Esaki Diodes. Four Esaki diode structures were fabricated and measured, with current densities up to 1 kA/cm2. Peak-to-valley current ratios up to 56 have been achieved, which is greater than twice that of the best GaAs Esaki Diodes previously reported.
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monolithically integrated si sige resonant interband Tunnel diode cmos demonstrating low voltage mobile operation
Solid-state Electronics, 2004Co-Authors: S Sudirgo, S L Rommel, R P Nandgaonkar, B Curanovic, J Hebding, R Saxer, Syed S Islam, K D Hirschman, S K Kurinec, Phillip E ThompsonAbstract:The first demonstration of the monolithic integration of CMOS and Si/SiGe resonant interband Tunnel Diodes (RITD) with negative differential resistance (NDR) is reported in this paper. The Si/SiGe RITDs exhibited a peak-tovalley current ratio (PVCR) up to 2.8 and peak current density (Jp) of 0.26 kA/cm 2 at room temperature. This study focused on the utilization of a pair of Tunnel Diodes connected in series to form a latch. Employing a FET to supply current into the latch, a RITD/NMOS monostable–bistable transition logic element (MOBILE) was realized. The latch exhibited a voltage swing of 84% at an applied supply voltage of 0.5 V. This logic element enables low voltage operation for high density circuit design of embedded memory.
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three terminal si based negative differential resistance circuit element with adjustable peak to valley current ratios using a monolithic vertical integration
Applied Physics Letters, 2004Co-Authors: Sungyong Chung, Phillip E Thompson, S L Rommel, Roger K Lake, Paul R Berger, Niu Jin, S K KurinecAbstract:Si-based resonant bipolar transistors are demonstrated by the monolithic vertical integration of Si-based resonant interband Tunnel Diodes atop the emitter of Si/SiGe heterojunction bipolar transistors (HBTs) on a silicon substrate. In the common emitter configuration, IC versus VCE shows negative differential resistance characteristics. The resulting characteristics are adjustable peak-to-valley current ratios, including infinite and negative values, and tailorable peak current densities by the control of the HBT base current under room temperature operation. With the integrated RITD-HBT combination, latching properties which are the key operating principle for high-speed mixed-signal, memory, and logic circuitry, are experimentally demonstrated.
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three terminal si based negative differential resistance circuit element with adjustable peak to valley current ratios using a monolithic vertical integration
Journal of Applied Physics, 2004Co-Authors: Sungyong Chung, Phillip E Thompson, S L Rommel, Roger K Lake, Paul R Berger, Niu Jin, S K KurinecAbstract:Si-based resonant bipolar transistors are demonstrated by the monolithic vertical integration of Si-based resonant interband Tunnel Diodes atop the emitter of Si/SiGe heterojunction bipolar transistors ~HBTs! on a silicon substrate. In the common emitter configuration, IC versus VCE shows negative differential resistance characteristics. The resulting characteristics are adjustable peak-to-valley current ratios, including infinite and negative values, and tailorable peak current densities by the control of the HBT base current under room temperature operation. With the integrated RITD-HBT combination, latching properties which are the key operating principle for high-speed mixed-signal, memory, and logic circuitry, are experimentally demonstrated. © 2004 American Institute of Physics. @DOI: 10.1063/1.1690109#
