The Experts below are selected from a list of 894 Experts worldwide ranked by ideXlab platform
Nanette Bauer - One of the best experts on this subject based on the ideXlab platform.
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algorithmic verification of logic controllers given as Sequential Function Charts
International Conference on Robotics and Automation, 2004Co-Authors: Manuel Remelhe, Sven Lohmann, Sebastian Engell, Olaf Stursberg, Nanette BauerAbstract:The a-posteriori analysis of logic controllers can be a suitable means to detect design flaws if the controller was not developed by a synthesis algorithm that correctly considered all relevant requirements. This paper advocates the verification of logic controllers with a special focus on the following three issues: (a) the control code is given as a Sequential Function Chart (SFC), a description language becoming increasingly popular for industrial controllers; (b) the cyclic operation mode of the hardware on which the controllers is implemented is taken into account; (c) specifications of the control logic that include timers and the real-time behavior of the controlled plant are considered. We propose an approach in which the SFC controller is first translated into a timed automaton using an algorithm that explores a special graph grammar. The automaton can then be composed with a timed automaton modeling the plant behavior, and model-checking of the composition reveals whether a given set of requirements is fulfilled. All steps of the procedure are illustrated for the example of a controlled evaporation system
Sebastian Engell - One of the best experts on this subject based on the ideXlab platform.
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Iterative Specification Refinement in Deriving Logic Controllers
Computer-aided chemical engineering, 2008Co-Authors: Sven Lohmann, Lan Anh Dinh Thi, Thanh Ha Tran, Olaf Stursberg, Sebastian EngellAbstract:Abstract In this paper the refinement procedure of informal requirements in the context of an earlier proposed systematic procedure for logic controller design as Sequential Function Chart (SFC) is described in detail. The use of two data formats is proposed: dependency Charts (DC) and Function tables (FT) that support hierarchy and modularization and are refined iteratively until a final degree of detail is reached from which the logic controller as SFC can be generated algorithmically.
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Systematic Logic Controller Design as Sequential Function Chart Starting from Informal Specifications
Chinese Journal of Chemical Engineering, 2008Co-Authors: Sven Lohmann, Sebastian EngellAbstract:Abstract Today's automation industry is driven by the need for an increased productivity, higher flexibility, and higher individuality, and characterized by tailor-made and more complex control solutions. In the processing industry, logic controller design is often a manual, experience-based, and thus an error-prone procedure. Typically, the specifications are given by a set of informal requirements and a technical flowChart and both are used to be directly translated into the control code. This paper proposes a method in which the control program is constructed as a Sequential Function Chart (SFC) by transforming the requirements via clearly defined intermediate formats. For the purpose of analysis, the resulting SFC can be translated algorithmically into timed automata. A rigorous verification can be used to determine whether all specifications are satisfied if a formal model of the plant is available which is then composed with the automata model of the logic controller (LC).
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algorithmic verification of logic controllers given as Sequential Function Charts
International Conference on Robotics and Automation, 2004Co-Authors: Manuel Remelhe, Sven Lohmann, Sebastian Engell, Olaf Stursberg, Nanette BauerAbstract:The a-posteriori analysis of logic controllers can be a suitable means to detect design flaws if the controller was not developed by a synthesis algorithm that correctly considered all relevant requirements. This paper advocates the verification of logic controllers with a special focus on the following three issues: (a) the control code is given as a Sequential Function Chart (SFC), a description language becoming increasingly popular for industrial controllers; (b) the cyclic operation mode of the hardware on which the controllers is implemented is taken into account; (c) specifications of the control logic that include timers and the real-time behavior of the controlled plant are considered. We propose an approach in which the SFC controller is first translated into a timed automaton using an algorithm that explores a special graph grammar. The automaton can then be composed with a timed automaton modeling the plant behavior, and model-checking of the composition reveals whether a given set of requirements is fulfilled. All steps of the procedure are illustrated for the example of a controlled evaporation system
Jan Olaf Blech - One of the best experts on this subject based on the ideXlab platform.
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Applying Model Checking to Industrial-Sized PLC Programs
IEEE Transactions on Industrial Informatics, 2015Co-Authors: Borja Fernández Adiego, Jan Olaf Blech, Dániel Darvas, Enrique Blanco Viñuela, Jean-charles Tournier, Simon Bliudze, Víctor Manuel González SuárezAbstract:Programmable logic controllers (PLCs) are embedded computers widely used in industrial control systems. Ensuring that a PLC software complies with its specification is a challenging task. Formal verification has become a recommended practice to ensure the correctness of safety-critical software, but is still underused in industry due to the complexity of building and managing formal models of real applications. In this paper, we propose a general methodology to perform automated model checking of complex properties expressed in temporal logics [e.g., computation tree logic (CTL) and linear temporal logic (LTL)] on PLC programs. This methodology is based on an intermediate model (IM) meant to transform PLC programs written in various standard languages [structured text (ST), Sequential Function Chart (SFC), etc.] to different modeling languages of verification tools. We present the syntax and semantics of the IM, and the transformation rules of the ST and SFC languages to the nuXmv model checker passing through the IM. Finally, two real cases studies of the European Organization for Nuclear Research (CERN) PLC programs, written mainly in the ST language, are presented to illustrate and validate the proposed approach.
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A Tool for the Certification of Sequential Function Chart based System Specifications
2012Co-Authors: Jan Olaf BlechAbstract:We describe a tool framework for certifying properties of Sequential Function Chart (SFC)based system specifications: CertPLC. CertPLC handles programmable logic controller (PLC) descriptions provided in the SFC language of the IEC 61131–3 standard. It provides routines to certify properties of systems by delivering an independently checkable formal system description and proof (called certificate) for the desired properties. We focus on properties that can be described as inductive invariants. System descriptions and certificates are generated and handled using the Coq proof assistant. Our tool framework is used to provide supporting evidence for the safety of embedded systems in the industrial automation domain to third-party authorities. In this paper we focus on the tool's architecture, requirements and implementation aspects.
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A Tool for the Certification of PLCs based on a Coq Semantics for Sequential Function Charts
arXiv: Software Engineering, 2011Co-Authors: Jan Olaf BlechAbstract:In this report we describe a tool framework for certifying properties of PLCs: CERTPLC. CERTPLC can handle PLC descriptions provided in the Sequential Function Chart (SFC) language of the IEC 61131-3 standard. It provides routines to certify properties of systems by delivering an independently checkable formal system description and proof (called certificate) for the desired properties. We focus on properties that can be described as inductive invariants. System descriptions and certificates are generated and handled using the COQ proof assistant. Our tool framework is used to provide supporting evidence for the safety of embedded systems in the industrial automation domain to third-party authorities. In this document we describe the tool framework: usage scenarios, the archi-tecture, semantics of PLCs and their realization in COQ, proof generation and the construction of certificates.
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SSV - A tool for the certification of Sequential Function Chart based system specifications
2011Co-Authors: Jan Olaf BlechAbstract:We describe a tool framework for certifying properties of Sequential Function Chart (SFC) based system specifications: CERTPLC. CERTPLC handles programmable logic controller (PLC) descriptions provided in the SFC language of the IEC 61131-3 standard. It provides routines to certify properties of systems by delivering an independently checkable formal system description and proof (called certificate) for the desired properties. We focus on properties that can be described as inductive invariants. System descriptions and certificates are generated and handled using the COQ proof assistant. Our tool framework is used to provide supporting evidence for the safety of embedded systems in the industrial automation domain to third-party authorities. In this paper we focus on the tool's architecture, requirements and implementation aspects.
Jean-marc Roussel - One of the best experts on this subject based on the ideXlab platform.
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test sequence construction from sfc specification
IFAC Proceedings Volumes, 2009Co-Authors: Julien Provost, Jean-marc Roussel, Jeanmarc FaureAbstract:This paper focuses on conformance test of electronic programmable devices whose specification is given in Sequential Function Chart (SFC). More precisely, a method is proposed to obtain automatically, from this specification, one minimum length test sequence which permits the exhaustive test of the behavior of the device. This method takes advantage of previous results on construction of the state machine representation of a SFC and on test of Mealy machines; conversely, it extends the industrial use possibilities of this latter technique. The contribution is exemplified on a simple model.
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Author manuscript, published in "9th International Workshop On Discrete Event Systems (WODES'08), Göteborg: Suède (2008)" Algebraic Synthesis of Transition Conditions of a State Model
2009Co-Authors: Yann Hietter, Jean-marc Roussel, Jean-jacques Lesage Ieee MemberAbstract:Abstract — The synthesis method presented in this paper has been developed to automatically design logic controllers. In this paper, we show how to use this approach in the specific case where a designer must derive a particular controller from a generic model. The instantiation of the model is completely achieved by an algebraic synthesis. To illustrate the approach, the example of a water supply system is used and the generic model of the controller is given under the form of a Sequential Function Chart (SFC). I
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Author manuscript, published in "IMACS-IEEE "CESA'96", Lille: France (1996)" Validation and Verification of grafcets using finite state machine
2009Co-Authors: Jean-marc Roussel, Jean-jacques LesageAbstract:This paper presents a method to verify (the internal consistency) and to validate (with respect to the purpose of the builders) Sequential Function Charts [8] (grafcets in French). The method is based upon the translation of any grafcet into its equivalent finite automaton. The proofs of consistency of the models are then established on this automaton. The main difficulty of this approach is the control of the combinatorial explosion implied by the parallel and the synchronous nature of Grafcet. A specific grammar has been developed in order to express the expected properties to prove. An example is given to illustrate the presented approach. Key-Words: Sequential Function Chart (S.F.C.), Grafcet, validation, verification, reachable situations graph, finite state machine. 1
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Algebraic Synthesis of Transition Conditions of a State Model
2008Co-Authors: Yann Hietter, Jean-marc Roussel, Jean-jacques LesageAbstract:The synthesis method presented in this paper has been developed to automatically design logic controllers. In this paper, we show how to use this approach in the specific case where a designer must derive a particular controller from a generic model. The instantiation of the model is completely achieved by an algebraic synthesis. To illustrate the approach, the example of a water supply system is used and the generic model of the controller is given under the form of a Sequential Function Chart (SFC).
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A Theory of Binary Signal
1996Co-Authors: Jean-jaques Lesage, Jean-marc Roussel, Christophe ThierryAbstract:The dynamic modelling of logical systems widely calls upon the explicit use of time and the event notion. In terms of Function Chart Grafcet or Interpreted Petri Nets for instance, events are generally represented by "rising or falling edges" of logical variables. However, numerous ambiguities are encountered in the models because the translation of events into edges is not formal enough. In this paper, we propose a theory of binary signal which allows us to describe the time behavior of the inputs and the outputs of any logical system. We especially describe an extended Boolean Algebra. In this algebra, we have defined two unary operations in order to formally express the events. Then, we give ten properties related to these rising and falling edge operations and their composition with the operations AND, OR, and NOT. Key-Words: Sequential Function Chart (S.F.C.), Grafcet, binary signal, event, boolean algebra, logical system. 1. INTRODUCTION The notion of event is widely used in d..
Sven Lohmann - One of the best experts on this subject based on the ideXlab platform.
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Iterative Specification Refinement in Deriving Logic Controllers
Computer-aided chemical engineering, 2008Co-Authors: Sven Lohmann, Lan Anh Dinh Thi, Thanh Ha Tran, Olaf Stursberg, Sebastian EngellAbstract:Abstract In this paper the refinement procedure of informal requirements in the context of an earlier proposed systematic procedure for logic controller design as Sequential Function Chart (SFC) is described in detail. The use of two data formats is proposed: dependency Charts (DC) and Function tables (FT) that support hierarchy and modularization and are refined iteratively until a final degree of detail is reached from which the logic controller as SFC can be generated algorithmically.
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Systematic Logic Controller Design as Sequential Function Chart Starting from Informal Specifications
Chinese Journal of Chemical Engineering, 2008Co-Authors: Sven Lohmann, Sebastian EngellAbstract:Abstract Today's automation industry is driven by the need for an increased productivity, higher flexibility, and higher individuality, and characterized by tailor-made and more complex control solutions. In the processing industry, logic controller design is often a manual, experience-based, and thus an error-prone procedure. Typically, the specifications are given by a set of informal requirements and a technical flowChart and both are used to be directly translated into the control code. This paper proposes a method in which the control program is constructed as a Sequential Function Chart (SFC) by transforming the requirements via clearly defined intermediate formats. For the purpose of analysis, the resulting SFC can be translated algorithmically into timed automata. A rigorous verification can be used to determine whether all specifications are satisfied if a formal model of the plant is available which is then composed with the automata model of the logic controller (LC).
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algorithmic verification of logic controllers given as Sequential Function Charts
International Conference on Robotics and Automation, 2004Co-Authors: Manuel Remelhe, Sven Lohmann, Sebastian Engell, Olaf Stursberg, Nanette BauerAbstract:The a-posteriori analysis of logic controllers can be a suitable means to detect design flaws if the controller was not developed by a synthesis algorithm that correctly considered all relevant requirements. This paper advocates the verification of logic controllers with a special focus on the following three issues: (a) the control code is given as a Sequential Function Chart (SFC), a description language becoming increasingly popular for industrial controllers; (b) the cyclic operation mode of the hardware on which the controllers is implemented is taken into account; (c) specifications of the control logic that include timers and the real-time behavior of the controlled plant are considered. We propose an approach in which the SFC controller is first translated into a timed automaton using an algorithm that explores a special graph grammar. The automaton can then be composed with a timed automaton modeling the plant behavior, and model-checking of the composition reveals whether a given set of requirements is fulfilled. All steps of the procedure are illustrated for the example of a controlled evaporation system
