The Experts below are selected from a list of 66 Experts worldwide ranked by ideXlab platform
Steve Leibson - One of the best experts on this subject based on the ideXlab platform.
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The Diamond Standard Series 108Mini Processor Core
Designing SOCs with Configured Cores, 2006Co-Authors: Steve LeibsonAbstract:The Diamond Standard Series 108Mini Processor core is the smallest of the Diamond Standard Series Processor cores. The Processor consumes less than 0.5 mm 2 of silicon and approximately 110 μW/MHz when implemented in a 130 nm, G-type (general purpose) process technology. Although the 108Mini Processor core is physically small, it is still a full featured, 32-bit RISC Processor that can run any program compiled by the Diamond Edition XCC C/C + + compiler, and it can run real-time operating systems (RTOSs) such as the Nucleus Plus RTOS from Accelerated Technology. The Diamond 108Mini suits the roles assigned to 8- and 16-bit controller cores but it brings many performance benefits of a 32-bit Processor to bear on the designated tasks: large 4-Gbyte address space and 32-bit computations. The Diamond 108Mini Processor core has a 32-bit version of the general purpose Processor interface bus for global system-on-chip communications, but it is intended to be used as a control Processor that executes code from local instruction memory and accesses data primarily from local data memories.
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Introduction to Diamond Standard Series Processor Cores
Designing SOCs with Configured Cores, 2006Co-Authors: Steve LeibsonAbstract:This chapter presents an introduction to diamond standard Series Processor cores. With their configurability and extensibility, Tensilica's 32-bit Xtensa microProcessor cores can perform a very wide array of system-on-chip (SOC) tasks. These cores, comprising the Diamond Standard Series of preconfigured cores, offer a wide range of performance options without the need to further configure them. Diamond Processor cores employ the Xtensa instruction-set architecture (ISA), so they are software compatible with the configurable Xtensa cores and use the same software-development tools. They carry on the Xtensa system-design philosophy of moving the bulk of a system's capabilities into firmware and defining those capabilities through application code written in C or C + + as much as possible for the maximum flexibility and easier system maintenance. In addition to being extremely useful system components for SOC designs, the Diamond Processor cores also demonstrate several interesting dimensions of Xtensa configurable-core technology.
Kai Long Wang - One of the best experts on this subject based on the ideXlab platform.
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a dual core operating system framework based on autosar os for hcs12x Series Processor
International Conference on Robotics and Automation, 2014Co-Authors: Jian Chun Jiang, Kai Long WangAbstract:One kind of Processors with coProcessor is widely used in control areas. Traditional single-core operating system (OS) cant support the coProcessor. In order to take full advantage of the performance of the Processor, we presented a real-time operating system framework named AutoOSEK-CP on the basis of AutoOSEK, which is a single-core operating system based on AutoSAR OS, to support dual-core Processor. In this architecture, alarm management, interrupt processing and inter-core communication mechanism were moved in coProcessor module, and the master Processor was responsible for the other functions of OS. Finally, we designed a prototype of AutoOSEK-CP to test the performance in HCS12XEP100. The results showed that the real-time performance and the time-tick accuracy were improved significantly compared with AutoOSEK.
E. D. Kuznetsov - One of the best experts on this subject based on the ideXlab platform.
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the construction of averaged planetary motion theory by means of computer algebra system piranha
arXiv: Instrumentation and Methods for Astrophysics, 2018Co-Authors: A. S. Perminov, E. D. KuznetsovAbstract:The application of computer algebra system Piranha to the investigation of the planetary problem is described in this work. Piranha is an echeloned Poisson Series Processor authored by F. Biscani from Max Planck Institute for Astronomy in Heidelberg. Using Piranha the averaged semi-analytical motion theory of four-planetary system is constructed up to the second degree of planetary masses. In this work we use the algorithm of the Hamiltonian expansion into the Poisson Series in only orbital elements without other variables. The motion equations are obtained analytically in time-averaged elements by Hori-Deprit method. Piranha showed high-performance of analytical manipulations. Different properties of obtained Series are discussed. The numerical integration of the motion equations is performed by Everhart method for the Solar system's giant-planets and some exoplanetary systems.
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the use of cas piranha for the construction of motion equations of the planetary system problem
Special Sessions in Applications of Computer Algebra, 2015Co-Authors: A. S. Perminov, E. D. KuznetsovAbstract:In this paper, we consider the using of the computer algebra system Piranha as applied to the study of the planetary problem. Piranha is an echeloned Poisson Series Processor, which is written in C++ language. It is new, specified, high-efficient program for analytical transformations of polynomials, Fourier and Poisson Series. We used Piranha for the expansion of the Hamiltonian of four-planetary problem into the Poisson Series and the construction of motion equations by the Hori–Deprit method. Both of these algorithms are briefly presented in this work. Different properties of the Series representation of the Hamiltonian and motion equations are discussed.
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expansion of the hamiltonian of the two planetary problem into the poisson Series in all elements application of the poisson Series Processor
Solar System Research, 2004Co-Authors: E. D. Kuznetsov, K V KholshevnikovAbstract:This paper is the third in a Series of articles devoted to one of the basic problems of celestial mechanics: the study of the evolution of solar-type planetary systems. In the previous papers a brief review of the history and current state of the problem was given; the plan of the study was outlined; the Jacobi coordinates and the related osculating elements were introduced; the form of the Poisson expansion of the Hamiltonian in all elements was given; and the expansion coefficients for the Hamiltonian of the two-planetary Sun–Jupiter–Saturn problem were obtained (though with impure accuracy) by a simple algorithm that is reduced to the calculation of multiple integrals of elementary functions. In the present paper the expansion of the Hamiltonian of the two-planetary Sun–Jupiter–Saturn problem into the Poisson Series in all elements is constructed with the help of the PSP Poisson Series Processor, which is capable of required accuracy.
Jian Chun Jiang - One of the best experts on this subject based on the ideXlab platform.
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a dual core operating system framework based on autosar os for hcs12x Series Processor
International Conference on Robotics and Automation, 2014Co-Authors: Jian Chun Jiang, Kai Long WangAbstract:One kind of Processors with coProcessor is widely used in control areas. Traditional single-core operating system (OS) cant support the coProcessor. In order to take full advantage of the performance of the Processor, we presented a real-time operating system framework named AutoOSEK-CP on the basis of AutoOSEK, which is a single-core operating system based on AutoSAR OS, to support dual-core Processor. In this architecture, alarm management, interrupt processing and inter-core communication mechanism were moved in coProcessor module, and the master Processor was responsible for the other functions of OS. Finally, we designed a prototype of AutoOSEK-CP to test the performance in HCS12XEP100. The results showed that the real-time performance and the time-tick accuracy were improved significantly compared with AutoOSEK.
Simmhan Yogesh - One of the best experts on this subject based on the ideXlab platform.
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ARM Wrestling with Big Data: A Study of Commodity ARM64 Server for Big Data Workloads
IEEE 345 E 47TH ST NEW YORK NY 10017 USA, 2017Co-Authors: Kalyanasundaram Jayanth, Simmhan YogeshAbstract:ARM Processors have dominated the mobile device market in the last decade due to their favorable computing to energy ratio. In this age of Cloud data centers and Big Data analytics, the focus is increasingly on power efficient processing, rather than just high throughput computing. ARM's first commodity server-grade Processor is the recent AMD A1100-Series Processor, based on a 64-bit ARM Cortex A57 architecture. In this paper, we study the performance and energy efficiency of a server based on this ARM64 CPU, relative to a comparable server running an AMD Opteron 3300-Series x64 CPU, for Big Data workloads. Specifically, we study these for Intel's HiBench suite of web, query and machine learning benchmarks on Apache Hadoop v2.7 in a pseudo-distributed setup, for data sizes up to 20GB files, 5M web pages and 500M tuples. Our results show that the ARM64 server's runtime performance is comparable to the x64 server for integer-based workloads like Sort and Hive queries, and only lags behind for floating-point intensive benchmarks like PageRank, when they do not exploit data parallelism adequately. We also see that the ARM64 server takes 1/3rd the energy, and has an Energy Delay Product (EDP) that is 50 - 71% lower than the x64 server. These results hold promise for ARM64 data centers hosting Big Data workloads to reduce their operational costs, while opening up opportunities for further analysis
