The Experts below are selected from a list of 6876 Experts worldwide ranked by ideXlab platform
B. Verghese - One of the best experts on this subject based on the ideXlab platform.
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Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000Co-Authors: L.a. Barroso, K. Gharachorloo, R. Mcnamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, B. VergheseAbstract:This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multiprocessing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.
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Piranha a scalable architecture based on single chip multiprocessing
International Symposium on Computer Architecture, 2000Co-Authors: L.a. Barroso, K. Gharachorloo, R. Mcnamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, B. VergheseAbstract:The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instruction-level parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors targeted at commercial servers. This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multi-processing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.
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ISCA - Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00, 2000Co-Authors: L.a. Barroso, K. Gharachorloo, R. Mcnamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, B. VergheseAbstract:The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instruction-level parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors targeted at commercial servers. This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multi-processing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.
Ki-sik Im - One of the best experts on this subject based on the ideXlab platform.
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dual surface modification of algan gan hemts using tmah and Piranha solutions for enhancing current and 1 f noise characteristics
IEEE Journal of the Electron Devices Society, 2018Co-Authors: Siva Pratap M. Reddy, Won-sang Park, Ki-sik ImAbstract:We demonstrated dual-surface modification of GaN/AlGaN/GaN high-electron mobility transistors using tetramethylammonium hydroxide (TMAH) and Piranha solutions prior to gate metallization. The TMAH-treated device exhibits improved performances with lower I-V hysteresis, in off-state leakage current and gate leakage current. The device performances were further significantly improved with applies additional Piranha solution treatment right after the TMAH treatment, especially in hysteresis and 1/f-noise characteristics. It is found that the Schottky barrier height is high and ideality factor is low measured from I-V characteristics for the TMAH and Piranha solution treated device. Reasonable gate leakage mechanisms were also discussed using Poole–Frenkel and Schottky emissions. In addition, it is observed that the magnitude of interface state density for the TMAH treatment after the Piranha solution treated device shows significantly low compared to other devices. These excellent device-performances are observed due to the reason of dual-surface treatment which effectively decreases the surface trap density with an appropriate etching and passivation of the device surface exposed prior to the gate metallization.
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Dual-Surface Modification of AlGaN/GaN HEMTs Using TMAH and Piranha Solutions for Enhancing Current and 1/f-Noise Characteristics
IEEE Journal of the Electron Devices Society, 2018Co-Authors: Siva Pratap M. Reddy, Won-sang Park, Ki-sik ImAbstract:We demonstrated dual-surface modification of GaN/AlGaN/GaN high-electron mobility transistors using tetramethylammonium hydroxide (TMAH) and Piranha solutions prior to gate metallization. The TMAH-treated device exhibits improved performances with lower I-V hysteresis, in off-state leakage current and gate leakage current. The device performances were further significantly improved with applies additional Piranha solution treatment right after the TMAH treatment, especially in hysteresis and 1/f-noise characteristics. It is found that the Schottky barrier height is high and ideality factor is low measured from I-V characteristics for the TMAH and Piranha solution treated device. Reasonable gate leakage mechanisms were also discussed using Poole-Frenkel and Schottky emissions. In addition, it is observed that the magnitude of interface state density for the TMAH treatment after the Piranha solution treated device shows significantly low compared to other devices. These excellent device-performances are observed due to the reason of dual-surface treatment which effectively decreases the surface trap density with an appropriate etching and passivation of the device surface exposed prior to the gate metallization.
Sven Tengeler - One of the best experts on this subject based on the ideXlab platform.
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the 001 3c sic surface termination and band structure after common wet chemical etching procedures stated by xps leed and hreels
Applied Surface Science, 2018Co-Authors: Sven Tengeler, Bernhard Kaiser, Gabriel Ferro, Didier Chaussende, W JaegermannAbstract:The (001) surface of cubic silicon carbide (3C SiC) after cleaning, Ar sputtering and three different wet chemical etching procedures was thoroughly investigated via (angle resolved) XPS, HREELS, and LEED. While Ar sputtering was found to be unsuitable for surface preparation, all three employed wet chemical etching procedures (Piranha/NH4F, Piranha/HF, and RCA) provide a clean surface. HF as oxide removal agent tends to result in fluorine traces on the sample surface, despite thorough rinsing. All procedures yield a 1 × 1 Si–OH/C–H terminated surface. However, the XPS spectra reveal some differences in the resulting surface states. NH4F for oxide removal produces a flat band situation, whereas the other two procedures result in a slight downward (HF) or upward (RCA) band bending. Because the band bending is small, it can be concluded that the number of unsaturated surface defects is low.
Sandeep Kranthi A Kiran - One of the best experts on this subject based on the ideXlab platform.
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modulation of biological properties by grain refinement and surface modification on titanium surfaces for implant related infections
Journal of Materials Science, 2019Co-Authors: Sandeep Kranthi A Kiran, T Sampath S Kumar, Mukesh Doble, Merum Sireesha, Raghavendra Ramalingam, Atish Kizhakeyil, Navin Kumar Verma, Rajamani Lakshminarayanan, Seeram RamakrishnaAbstract:The nanostructured titanium (Ti) obtained by the equal-channel angular pressing (ECAP) has shown great promise as a biomedical implant material over the past few decades. The present work aims to investigate the effect of topographical changes caused by ECAP and Piranha treatment (Tr) on the surface performance and biological properties of Ti for bone tissue engineering applications. The effects of dual treatments, i.e., ECAP and Tr, on Ti were systematically investigated by multiple characterization techniques, surface wettability, apatite-forming ability, cellular behavior, and antibacterial studies. We demonstrate that both ECAP and ECApTr samples possess desirable mechanical and physical properties and are biocompatible to cultured human fetal osteoblast (hFOB) cells. The potential of adhesion and proliferation of hFOB cells on ECAP and ECApTr samples was found to be superior to that of control unprocessed sample (annealed). Ti samples prepared by both methods showed excellent antimicrobial properties against clinical strains of the most common pathogenic bacteria causing orthopedic implant infections, Staphylococcus aureus (S. aureus) and Pseudomonas aeruginosa (P. aeruginosa). This study supports the established claim about mechanical properties improvement by ultrafine refinement and further enhances the antibacterial properties when chemically etched with a Piranha solution.
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dual nanofibrous bioactive coating and antimicrobial surface treatment for infection resistant titanium implants
Progress in Organic Coatings, 2018Co-Authors: Sandeep Kranthi A Kiran, T Sampath S Kumar, Govindaraj Perumal, Rutvi Sanghavi, Mukesh Doble, Seeram RamakrishnaAbstract:Abstract Failures of biomedical implants due to implant-related infections and implant loosening remains a major concern in orthopaedic fixations. The current work aims to address the issues by examining the effect of dual interaction i.e surface modification and surface coatings on orthopaedic implant materials, i.e. commercially pure titanium (cpTi). The cpTi surface was initially modified with Piranha solution (H 2 SO 4 + H 2 O 2 ) to create an antibacterial surface. Further, the biological properties similar to bone tissue were improved by electrospun coating on the Piranha treated substrate with poly(e-caprolactone)(PCL)/hydroxyapatite (HA) composite nanofibers. The PCL/HA composite nanofibers have been characterized using SEM, XRD, EDS contact angle measurements, and FTIR spectroscopy. The coating adhesion of PCL/HA on cpTi was evaluated by cross-cut tape test (ASTM D3359-09). The newly fabricated substrates showed favourable properties and higher wettability. The antibacterial tests on Piranha treated nanostructured substrates also confirmed a substantial reduction in bacterial growth over large areas. Cellular interactive responses such as adhesive and proliferation of osteosarcoma MG-63 cell lines has also demonstrated that presence of PCL/HA electrospun coating on the modified surface have improved the biological properties. The currently developed Piranha treated and PCL/HA nanocomposite coated cpTi substrates seems to be a promising method to obtain both antibacterial and bioactive titanium surfaces.
L.a. Barroso - One of the best experts on this subject based on the ideXlab platform.
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Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000Co-Authors: L.a. Barroso, K. Gharachorloo, R. Mcnamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, B. VergheseAbstract:This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multiprocessing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.
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Piranha a scalable architecture based on single chip multiprocessing
International Symposium on Computer Architecture, 2000Co-Authors: L.a. Barroso, K. Gharachorloo, R. Mcnamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, B. VergheseAbstract:The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instruction-level parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors targeted at commercial servers. This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multi-processing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.
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ISCA - Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00, 2000Co-Authors: L.a. Barroso, K. Gharachorloo, R. Mcnamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, B. VergheseAbstract:The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instruction-level parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors targeted at commercial servers. This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multi-processing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.