The Experts below are selected from a list of 99474 Experts worldwide ranked by ideXlab platform
Marian K. Kazimierczuk - One of the best experts on this subject based on the ideXlab platform.
-
open loop power stage transfer functions relevant to current mode control of boost pwm converter operating in ccm
IEEE Transactions on Circuits and Systems I-regular Papers, 2005Co-Authors: B Bryant, Marian K. KazimierczukAbstract:This paper presents the analysis of open-loop power-stage dynamics relevant to current-mode control for a boost pulsewidth-modulated (PWM) dc-dc converter operating in continuous-conduction mode (CCM). The transfer functions from input voltage to inductor current, from duty cycle to inductor current, and from output current to inductor current are derived. The delay from the MOSFET gate drive to the duty cycle is modeled using a first-order Pade/spl acute/ approximation. The derivations are performed using an averaged linear small-Signal Circuit model of the boost converter for CCM. The transfer functions can be used in modeling the complete boost PWM converter when current-mode control is used. The theory was in excellent agreement with the experimental results, enforcing the validity of the transfer functions derived.
-
Small-Signal model of PWM converters for discontinuous conduction mode and its application for boost converter
IEEE Transactions on Circuits and Systems I-regular Papers, 2003Co-Authors: Alberto Reatti, Marian K. KazimierczukAbstract:A small-Signal Circuit model for pulsewidth-modulated DC-DC converters operated in discontinuous conduction mode is presented. The model is composed of controlled current sources, an independent voltage source and resistances. The principle of energy conservation approach is used to take into account parasitic resistances of the transistor and diode and the diode threshold voltage. The proposed model is suitable for small-Signal, frequency-domain representation of the converters. This model is used to derive the expressions for a boost converter control-to-output transfer function, input-to-output voltage transfer function, input impedance and the output impedance. Bode plots are also given for these transfer functions. The predicted and experimental results were in excellent agreement.
-
dynamic performance of pwm dc dc boost converter with input voltage feedforward control
IEEE Transactions on Circuits and Systems I-regular Papers, 1999Co-Authors: Marian K. Kazimierczuk, L A StarmanAbstract:Small-Signal characteristics are studied for a pulse-width modulated (PWM) boost converter with input voltage feedforward control. The characteristics are valid for the continuous conduction mode (CCM). A small-Signal Circuit model is used to derive the input-to-output voltage transfer function (audio-susceptibility), the input impedance, and the output impedance. A response of the output voltage to a step change in the input voltage is also computed. The measured Bode plots of the input-to-output voltage transfer function agreed with that predicted theoretically. It is shown that the feedforward control may reduce the magnitude of the input-to-output voltage transfer function by 40 dB. The input resistance of the converter with feedforward control is negative at low frequencies. The output impedance is not affected by feedforward control.
-
energy conservation approach to modeling pwm dc dc converters
IEEE Transactions on Aerospace and Electronic Systems, 1993Co-Authors: Dariusz Czarkowski, Marian K. KazimierczukAbstract:A systematic method is presented for including parasitic resistances and offset voltage sources of power switches in averaged dynamic large-Signal, DC, and small-Signal Circuit models of pulse-width modulated (PWM) converters operating in continuous conduction mode (CCM). This method is based on the principle of energy conservation. The approach takes into account the inductor current ripple. For zero-ripple current, the method gives the same results as the state-space averaging method. Reflection rules are introduced and used to simplify the models. As an example, a modeling procedure for the PWM buck converter is detailed. >
A Ripp - One of the best experts on this subject based on the ideXlab platform.
-
dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed Signal Circuit design
Design Automation and Test in Europe, 2006Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A RippAbstract:The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until now -- Circuit design, physical design and manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated Circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured Circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-Signal Circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -- both for digital as well as for analog is a big challenge. Yield analysis and optimization is currently applied to individual Circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (On Chip Variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6σ). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.
-
date 2006 special session dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed Signal Circuit design
Design Automation and Test in Europe, 2006Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A RippAbstract:The concepts of design for manufacturability and design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $Circuit design, physical design and manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated Circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured Circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-Signal Circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual Circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6sigma). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices
Patrik Pribytny - One of the best experts on this subject based on the ideXlab platform.
-
Advanced Methodology for Fast 3-D TCAD Device/Circuit Electrothermal Simulation and Analysis of Power HEMTs
IEEE Transactions on Electron Devices, 2015Co-Authors: Ales Chvala, Daniel Donoval, Juraj Marek, Marian Molnar, Alexander Satka, Patrik PribytnyAbstract:This paper introduces an advanced methodology for fast 3-D Technology Computer Aided Design (TCAD) electrothermal simulation for the analysis of power devices. The proposed methodology is based on coupling finite element method (FEM) thermal and Circuit electrical simulation in a mixed-mode setup. A power InAlN/GaN high-electron mobility transistor (HEMT) is used to perform validation of the designed electrothermal simulation. A new equivalent temperature-dependent nonlinear analytical large Signal Circuit model of HEMT is proposed. The model is implemented to Synopsys TCAD Sentaurus using compact model interface. The designed electrothermal simulation methodology is developed to shorten the simulation time for complex 3-D devices. This approach combines the speed and accuracy, and couples temperature nonuniformity to the active device electrothermal behavior. The simulation results are compared with the measured data and results of 2-D FEM simulations. The features and limitations of the methods are analyzed and presented.
-
advanced methodology for fast 3 d tcad device Circuit electrothermal simulation and analysis of power hemts
IEEE Transactions on Electron Devices, 2015Co-Authors: Ales Chvala, Daniel Donoval, Juraj Marek, Marian Molnar, Alexander Satka, Patrik PribytnyAbstract:This paper introduces an advanced methodology for fast 3-D Technology Computer Aided Design (TCAD) electrothermal simulation for the analysis of power devices. The proposed methodology is based on coupling finite element method (FEM) thermal and Circuit electrical simulation in a mixed-mode setup. A power InAlN/GaN high-electron mobility transistor (HEMT) is used to perform validation of the designed electrothermal simulation. A new equivalent temperature-dependent nonlinear analytical large Signal Circuit model of HEMT is proposed. The model is implemented to Synopsys TCAD Sentaurus using compact model interface. The designed electrothermal simulation methodology is developed to shorten the simulation time for complex 3-D devices. This approach combines the speed and accuracy, and couples temperature nonuniformity to the active device electrothermal behavior. The simulation results are compared with the measured data and results of 2-D FEM simulations. The features and limitations of the methods are analyzed and presented.
Markus Buhler - One of the best experts on this subject based on the ideXlab platform.
-
dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed Signal Circuit design
Design Automation and Test in Europe, 2006Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A RippAbstract:The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until now -- Circuit design, physical design and manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated Circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured Circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-Signal Circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -- both for digital as well as for analog is a big challenge. Yield analysis and optimization is currently applied to individual Circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (On Chip Variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6σ). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.
-
date 2006 special session dfm dfy design for manufacturability and yield influence of process variations in digital analog and mixed Signal Circuit design
Design Automation and Test in Europe, 2006Co-Authors: Markus Buhler, Juergen Koehl, Jeanne Paulette Bickford, Jason D Hibbeler, Michael Pronath, Ulf Schlichtmann, R. Sommer, A RippAbstract:The concepts of design for manufacturability and design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $Circuit design, physical design and manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated Circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured Circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-Signal Circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual Circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6sigma). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices
Ales Chvala - One of the best experts on this subject based on the ideXlab platform.
-
Advanced Methodology for Fast 3-D TCAD Device/Circuit Electrothermal Simulation and Analysis of Power HEMTs
IEEE Transactions on Electron Devices, 2015Co-Authors: Ales Chvala, Daniel Donoval, Juraj Marek, Marian Molnar, Alexander Satka, Patrik PribytnyAbstract:This paper introduces an advanced methodology for fast 3-D Technology Computer Aided Design (TCAD) electrothermal simulation for the analysis of power devices. The proposed methodology is based on coupling finite element method (FEM) thermal and Circuit electrical simulation in a mixed-mode setup. A power InAlN/GaN high-electron mobility transistor (HEMT) is used to perform validation of the designed electrothermal simulation. A new equivalent temperature-dependent nonlinear analytical large Signal Circuit model of HEMT is proposed. The model is implemented to Synopsys TCAD Sentaurus using compact model interface. The designed electrothermal simulation methodology is developed to shorten the simulation time for complex 3-D devices. This approach combines the speed and accuracy, and couples temperature nonuniformity to the active device electrothermal behavior. The simulation results are compared with the measured data and results of 2-D FEM simulations. The features and limitations of the methods are analyzed and presented.
-
advanced methodology for fast 3 d tcad device Circuit electrothermal simulation and analysis of power hemts
IEEE Transactions on Electron Devices, 2015Co-Authors: Ales Chvala, Daniel Donoval, Juraj Marek, Marian Molnar, Alexander Satka, Patrik PribytnyAbstract:This paper introduces an advanced methodology for fast 3-D Technology Computer Aided Design (TCAD) electrothermal simulation for the analysis of power devices. The proposed methodology is based on coupling finite element method (FEM) thermal and Circuit electrical simulation in a mixed-mode setup. A power InAlN/GaN high-electron mobility transistor (HEMT) is used to perform validation of the designed electrothermal simulation. A new equivalent temperature-dependent nonlinear analytical large Signal Circuit model of HEMT is proposed. The model is implemented to Synopsys TCAD Sentaurus using compact model interface. The designed electrothermal simulation methodology is developed to shorten the simulation time for complex 3-D devices. This approach combines the speed and accuracy, and couples temperature nonuniformity to the active device electrothermal behavior. The simulation results are compared with the measured data and results of 2-D FEM simulations. The features and limitations of the methods are analyzed and presented.