The Experts below are selected from a list of 228 Experts worldwide ranked by ideXlab platform

S.r. Bowes - One of the best experts on this subject based on the ideXlab platform.

  • Regular-sampled harmonic-elimination PWM control of inverter drives
    IEEE Transactions on Power Electronics, 1995
    Co-Authors: S.r. Bowes, P.r. Clark
    Abstract:

    Novel harmonic elimination PWM strategies for drives, uninterruptible power supplies and static power converters have been developed using modified regular-sampling techniques. These new PWM strategies can be generated on-line in real-time using a Simple Microprocessor software algorithm, without resorting to the usual time consuming off-line mainframe computer harmonic elimination numerical techniques. These new PWM techniques can be used over the complete voltage/frequency range of the drive up to and including the transition from PWM to quasi-square wave operation. Results from an experimental Microprocessor controlled PWM inverter drive are presented to demonstrate and confirm the special feature of the new regular-sampled harmonic elimination PWM control strategies.

  • Simple Microprocessor implementation of new regular-sampled harmonic elimination PWM techniques
    IEEE Transactions on Industry Applications, 1992
    Co-Authors: S.r. Bowes, P.r. Clark
    Abstract:

    Harmonic elimination PWM strategies for electric drives and static power converters have recently been developed using modified regular sampling techniques. These new PWM strategies can be generated online in real time using a Simple Microprocessor software algorithm without resorting to the usual offline mainframe computer harmonic elimination numerical techniques. The implementation and generation of these new PWM techniques are presented using an INMOS transputer, although the same techniques can be performed on any standard 8 or 16 b Microprocessor. Results from an experimental transputer-controlled PWM inverter drive are presented to demonstrate and confirm the operation of the new regular sampled harmonic elimination PWM control strategies.

  • Transputer-based optimal PWM control of inverter drives
    IEEE Transactions on Industry Applications, 1992
    Co-Authors: S.r. Bowes, P.r. Clark
    Abstract:

    New optimal PWM strategies for voltage source inverter (VSI) drives have been developed using modified regular sampling techniques. These new PWM strategies can be generated online in real time using a Simple Microprocessor software algorithm without resorting to the usual offline mainframe computer minimization techniques. Using these optimal regular sampling PWM techniques, it is possible to produce a PWM drive performance that closely approximates optimized PWM performance up to quasi-square-wave operation. The implementation of these optimal PWM strategies on the INMOS transputer is discussed, and the performance is confirmed using experimental results from a transputer-controlled experimental PWM inverter induction motor drive system.

  • Transputer-based harmonic-elimination PWM control of inverter drives
    IEEE Transactions on Industry Applications, 1992
    Co-Authors: S.r. Bowes, P.r. Clark
    Abstract:

    Harmonic elimination PWM strategies for voltage source inverter and current source inverter (VSI and CSI) drives have been developed using modified regular sampling techniques. These strategies can be generated online in real time using a Simple Microprocessor software algorithm and can be used over the complete voltage/frequency range of the drive up to and including the transition from PWM to quasi-square wave (QSW) operation. The implementation and generation of these techniques using the parallel processing INMOS transputer are discussed, and the concurrency programming ability of the transputer for PWM generation is emphasized. The implementation of the new PWM strategy can also be performed on any standard 8 or 16 b Microprocessor using 4 or 1 timer implementations. Results from an experimental transputer-controlled PWM inverter drive are presented to demonstrate and confirm the special features of the new regular sampled harmonic elimination PWM control strategies.

  • Regular-sampled harmonic elimination/minimisation PWM techniques
    Fifth Annual Proceedings on Applied Power Electronics Conference and Exposition, 1990
    Co-Authors: S.r. Bowes
    Abstract:

    Recent development are surveyed in regular-sampled pulse width modulation (PWM) techniques which allow harmonic minimization and also harmonic elimination to be generated online in real-time using a Simple Microprocessor software algorithm. It is shown how, with suitable modification, the conventional regular-sampled PWM techniques can be simply extended to allow harmonic-minimization and also harmonic-elimination PWM to be closely reproduced using Simple algebraic equations. Using these optimal regular-sampling PWM techniques, it is possible to produce optimized PWM inverter drive, uninterruptible power supply, and static frequency converter performance, up to quasi-square-wave operation. All the detailed theory, mathematics, and equations needed to implement these new PWM strategies are presented, together with experimental results confirming the approach.

P.r. Clark - One of the best experts on this subject based on the ideXlab platform.

  • Regular-sampled harmonic-elimination PWM control of inverter drives
    IEEE Transactions on Power Electronics, 1995
    Co-Authors: S.r. Bowes, P.r. Clark
    Abstract:

    Novel harmonic elimination PWM strategies for drives, uninterruptible power supplies and static power converters have been developed using modified regular-sampling techniques. These new PWM strategies can be generated on-line in real-time using a Simple Microprocessor software algorithm, without resorting to the usual time consuming off-line mainframe computer harmonic elimination numerical techniques. These new PWM techniques can be used over the complete voltage/frequency range of the drive up to and including the transition from PWM to quasi-square wave operation. Results from an experimental Microprocessor controlled PWM inverter drive are presented to demonstrate and confirm the special feature of the new regular-sampled harmonic elimination PWM control strategies.

  • Transputer-based optimal PWM control of inverter drives
    IEEE Transactions on Industry Applications, 1992
    Co-Authors: S.r. Bowes, P.r. Clark
    Abstract:

    New optimal PWM strategies for voltage source inverter (VSI) drives have been developed using modified regular sampling techniques. These new PWM strategies can be generated online in real time using a Simple Microprocessor software algorithm without resorting to the usual offline mainframe computer minimization techniques. Using these optimal regular sampling PWM techniques, it is possible to produce a PWM drive performance that closely approximates optimized PWM performance up to quasi-square-wave operation. The implementation of these optimal PWM strategies on the INMOS transputer is discussed, and the performance is confirmed using experimental results from a transputer-controlled experimental PWM inverter induction motor drive system.

  • Simple Microprocessor implementation of new regular-sampled harmonic elimination PWM techniques
    IEEE Transactions on Industry Applications, 1992
    Co-Authors: S.r. Bowes, P.r. Clark
    Abstract:

    Harmonic elimination PWM strategies for electric drives and static power converters have recently been developed using modified regular sampling techniques. These new PWM strategies can be generated online in real time using a Simple Microprocessor software algorithm without resorting to the usual offline mainframe computer harmonic elimination numerical techniques. The implementation and generation of these new PWM techniques are presented using an INMOS transputer, although the same techniques can be performed on any standard 8 or 16 b Microprocessor. Results from an experimental transputer-controlled PWM inverter drive are presented to demonstrate and confirm the operation of the new regular sampled harmonic elimination PWM control strategies.

  • Transputer-based harmonic-elimination PWM control of inverter drives
    IEEE Transactions on Industry Applications, 1992
    Co-Authors: S.r. Bowes, P.r. Clark
    Abstract:

    Harmonic elimination PWM strategies for voltage source inverter and current source inverter (VSI and CSI) drives have been developed using modified regular sampling techniques. These strategies can be generated online in real time using a Simple Microprocessor software algorithm and can be used over the complete voltage/frequency range of the drive up to and including the transition from PWM to quasi-square wave (QSW) operation. The implementation and generation of these techniques using the parallel processing INMOS transputer are discussed, and the concurrency programming ability of the transputer for PWM generation is emphasized. The implementation of the new PWM strategy can also be performed on any standard 8 or 16 b Microprocessor using 4 or 1 timer implementations. Results from an experimental transputer-controlled PWM inverter drive are presented to demonstrate and confirm the special features of the new regular sampled harmonic elimination PWM control strategies.

  • Simple Microprocessor implementation of new regular-sampled harmonic elimination PWM techniques
    Conference Record of the 1990 IEEE Industry Applications Society Annual Meeting, 1990
    Co-Authors: S.r. Bowes, P.r. Clark
    Abstract:

    New harmonic elimination pulse-width-modulation (PWM) strategies for drives and static power converters have recently been developed using modified regular-sampling techniques. These new PWM strategies can be generated online in real time using a Simple Microprocessor software algorithm, without resorting to the usual offline mainframe computer harmonic elimination numerical techniques. The implementation and generation of these new PWM techniques are presented using the new INMOS transputer, although the same techniques can be performed on any standard 8 bit or 16 bit Microprocessor. Results from an experimental transputer-controlled PWM inverter drive are presented to demonstrate and confirm the operation of the new regular-sampled harmonic elimination PWM control strategies.

A. Amory - One of the best experts on this subject based on the ideXlab platform.

  • Asian Test Symposium - Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis
    Proceedings of the Ninth Asian Test Symposium, 2000
    Co-Authors: F. Vargas, A. Amory
    Abstract:

    We present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow this methodology is also used to perform an early-estimation of the obtained reliability level. Usually, this reliability estimation step is performed in the laboratory, by means of radiation facilities (particle accelerators). By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool (FT-PRO). Finally, we present also a case-study of a Simple Microprocessor used to analyze the FT-PRO performance in terms of the area overhead required to implement the fault-tolerant circuit.

  • Recent improvements on the specification of transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis
    Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843), 2000
    Co-Authors: F. Vargas, A. Amory
    Abstract:

    We present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow, this methodology is also used to perform an early-estimation of the obtained reliability level. Usually, this reliability estimation step is performed in the laboratory, by means of radiation facilities (particle accelerators). By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool (FT-PRO). Finally, we present also a case-study of a Simple Microprocessor used to analyze the FT-PRO performance in terms of the area overhead required to implement the fault-tolerant circuit.

  • Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis
    Proceedings of the Ninth Asian Test Symposium, 2000
    Co-Authors: F. Vargas, A. Amory
    Abstract:

    We present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow this methodology is also used to perform an early-estimation of the obtained reliability level. Usually, this reliability estimation step is performed in the laboratory, by means of radiation facilities (particle accelerators). By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool (FT-PRO). Finally, we present also a case-study of a Simple Microprocessor used to analyze the FT-PRO performance in terms of the area overhead required to implement the fault-tolerant circuit.

L. Claesen - One of the best experts on this subject based on the ideXlab platform.

  • Symbolic multi-level verification of refinement
    Proceedings Ninth Great Lakes Symposium on VLSI, 1999
    Co-Authors: S. Hendricx, L. Claesen
    Abstract:

    VLSI-system design can, in general, be characterized in terms of the step-wise refinement of intermediate solutions. Despite the fact that such refinements usually do not preserve time-scales, current formal verification approaches mostly start from the assumption that both specification and implementation utilize the same scales of time. Realizing the importance of being able to cope with differences in timing granularity, this preliminary paper proposes a symbolic methodology to verify that a low-level finite state machine is a refinement of a high-level finite state machine. To illustrate our approach, the step-wise refinement-and verification-of a Simple Microprocessor is presented.

  • Great Lakes Symposium on VLSI - Symbolic multi-level verification of refinement
    Proceedings Ninth Great Lakes Symposium on VLSI, 1999
    Co-Authors: S. Hendricx, L. Claesen
    Abstract:

    VLSI-system design can, in general, be characterized in terms of the step-wise refinement of intermediate solutions. Despite the fact that such refinements usually do not preserve time-scales, current formal verification approaches mostly start from the assumption that both specification and implementation utilize the same scales of time. Realizing the importance of being able to cope with differences in timing granularity, this preliminary paper proposes a symbolic methodology to verify that a low-level finite state machine is a refinement of a high-level finite state machine. To illustrate our approach, the step-wise refinement-and verification-of a Simple Microprocessor is presented.

F. Vargas - One of the best experts on this subject based on the ideXlab platform.

  • Asian Test Symposium - Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis
    Proceedings of the Ninth Asian Test Symposium, 2000
    Co-Authors: F. Vargas, A. Amory
    Abstract:

    We present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow this methodology is also used to perform an early-estimation of the obtained reliability level. Usually, this reliability estimation step is performed in the laboratory, by means of radiation facilities (particle accelerators). By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool (FT-PRO). Finally, we present also a case-study of a Simple Microprocessor used to analyze the FT-PRO performance in terms of the area overhead required to implement the fault-tolerant circuit.

  • Recent improvements on the specification of transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis
    Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843), 2000
    Co-Authors: F. Vargas, A. Amory
    Abstract:

    We present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow, this methodology is also used to perform an early-estimation of the obtained reliability level. Usually, this reliability estimation step is performed in the laboratory, by means of radiation facilities (particle accelerators). By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool (FT-PRO). Finally, we present also a case-study of a Simple Microprocessor used to analyze the FT-PRO performance in terms of the area overhead required to implement the fault-tolerant circuit.

  • Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis
    Proceedings of the Ninth Asian Test Symposium, 2000
    Co-Authors: F. Vargas, A. Amory
    Abstract:

    We present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow this methodology is also used to perform an early-estimation of the obtained reliability level. Usually, this reliability estimation step is performed in the laboratory, by means of radiation facilities (particle accelerators). By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool (FT-PRO). Finally, we present also a case-study of a Simple Microprocessor used to analyze the FT-PRO performance in terms of the area overhead required to implement the fault-tolerant circuit.