The Experts below are selected from a list of 45 Experts worldwide ranked by ideXlab platform

Michael Butler - One of the best experts on this subject based on the ideXlab platform.

  • Aggressive execution engines for surpassing Single Basic Block execution
    1993
    Co-Authors: Michael Butler
    Abstract:

    The increasing density of VLSI circuits has motivated research into ways to utilize large area budgets to improve computational performance. One promising approach is the exploitation of instruction-level parallelism. This technique is effective only if the amount of instruction-level parallelism present in real applications warrants it, and hardware can be designed to exploit it without sacrificing aggressive cycle times. Early studies suggested that sufficient parallelism exists in numeric applications, and more recent research efforts have concluded that sufficient parallelism exists in real, non-scientific applications to justify processors that will execute more than two instructions per cycle. These studies indicate significant performance improvements are possible using aggressive hardware designs today. Furthermore, they offer the possibility for substantial future gains from exploiting instruction-level parallelism using new microarchitectural models. This dissertation explores instruction-level parallelism and microarchitectural mechanisms to efficiently exploit it beyond what is currently thought to be available. The contributions of this dissertation include an extensive investigation into the availability of instruction-level parallelism, new techniques for exploiting the available parallelism, and insight into simulation methodologies. Preliminary trace-driven investigations demonstrate that a significant amount of parallelism is available for exploitation if the machine is designed to provide sufficient fetch bandwidth and high branch prediction accuracy. Experimental results indicate that dynamic scheduling provides a critical tolerance of imperfect memory hierarchies, but most dynamic selection mechanisms and instruction buffer organizations are adequate. In addition, an aggressive state maintenance mechanism provides a modest but consistent performance advantage. More aggressive hardware-based branch handling techniques provide modest performance improvements at significant hardware costs. These techniques demonstrate that further performance increases can be expected, but suggest that compiler support is required to reduce the hardware costs.

Kemal Ebcioglu - One of the best experts on this subject based on the ideXlab platform.

  • Making compaction-based parallelization affordable
    IEEE Transactions on Parallel and Distributed Systems, 1993
    Co-Authors: Toshio Nakatani, Kemal Ebcioglu
    Abstract:

    Compaction-based parallelization suffers from long compile time and large code size because of its inherent code explosion problem. If software pipelining is performed for loop parallelization along with compaction, as in the authors' compiler, the code explosion problem becomes more serious. The authors propose the software lookahead heuristic for use in software pipelining, which allows inter-Basic-Block movement of code within a prespecified number of operations, called the software lookahead window, on any path emanating from the currently processed instruction at compile time. Software lookahead enables instruction-level parallelism to be exploited in a much greater code area than a Single Basic Block, but the lookahead region is still limited to a constant depth by means of a user-specifiable window, and thus code explosion is restricted. The proposed scheme has been implemented in the authors' VLIW parallelizing compiler. To study the code explosion problem and instruction-level parallelism for branch-intensive code, they compiled five AIX utilities: sort, fgrep, sed, yacc, and compress. It is demonstrated that the software lookahead heuristic effectively alleviates the code explosion problem while successfully extracting a substantial amount of inter-Basic-Block parallelism. >

Haibing Guan - One of the best experts on this subject based on the ideXlab platform.

  • GCC - Efficient Online Trace Building Using Code Replication
    2010 Ninth International Conference on Grid and Cloud Computing, 2010
    Co-Authors: Haipeng Deng, Kai Chen, Bo Liu, Kan Zhou, Yindong Yang, Alei Liang, Haibing Guan
    Abstract:

    Hot trace building plays an important role in enhancing the performance of dynamic binary translators, since in most cases 10% of code takes 90% of execution time of the whole program. Hot traces can promote the code position to make better the locality of the code, therefore programs can achieve a better performance. Thus how to build qualified and long hot traces is the key point. Considering the situation when one Single Basic Block is needed by more than two hot traces, code replication can help build hot traces with cost of expansion of code size. In this paper, a code replication method to help with building hot traces as well as code positioning is presented, and experiments have been done to evaluate the details of changes that code replication brings to the system, like trace fragment length, memory size expansion, etc. With this method, a performance promotion by 0.5%-3.5% against the original trace building method has been achieved.

Toshio Nakatani - One of the best experts on this subject based on the ideXlab platform.

  • Making compaction-based parallelization affordable
    IEEE Transactions on Parallel and Distributed Systems, 1993
    Co-Authors: Toshio Nakatani, Kemal Ebcioglu
    Abstract:

    Compaction-based parallelization suffers from long compile time and large code size because of its inherent code explosion problem. If software pipelining is performed for loop parallelization along with compaction, as in the authors' compiler, the code explosion problem becomes more serious. The authors propose the software lookahead heuristic for use in software pipelining, which allows inter-Basic-Block movement of code within a prespecified number of operations, called the software lookahead window, on any path emanating from the currently processed instruction at compile time. Software lookahead enables instruction-level parallelism to be exploited in a much greater code area than a Single Basic Block, but the lookahead region is still limited to a constant depth by means of a user-specifiable window, and thus code explosion is restricted. The proposed scheme has been implemented in the authors' VLIW parallelizing compiler. To study the code explosion problem and instruction-level parallelism for branch-intensive code, they compiled five AIX utilities: sort, fgrep, sed, yacc, and compress. It is demonstrated that the software lookahead heuristic effectively alleviates the code explosion problem while successfully extracting a substantial amount of inter-Basic-Block parallelism. >

David J. Lilja - One of the best experts on this subject based on the ideXlab platform.

  • Exploiting the parallelism available in loops
    Computer, 1994
    Co-Authors: David J. Lilja
    Abstract:

    Because a loop's body often executes many times, loops provide a rich opportunity for exploiting parallelism. This article explains scheduling techniques and compares results on different architectures. Since parallel architectures differ in synchronization overhead, instruction scheduling constraints, memory latencies, and implementation details, determining the best approach for exploiting parallelism can be difficult. To indicate their performance potential, this article surveys several architectures and compilation techniques using a common notation and consistent terminology. First we develop the critical dependence ratio to determine a loop's maximum possible parallelism, given infinite hardware. Then we look at specific architectures and techniques. Loops can provide a large portion of the parallelism available in an application program, since the iterations of a loop may be executed many times. To exploit this parallelism, however, one must look beyond a Single Basic Block or a Single iteration for independent operations. The choice of technique depends on the underlying architecture of the parallel machine and the characteristics of each individual loop. >