The Experts below are selected from a list of 7680 Experts worldwide ranked by ideXlab platform
Katsumi Murase - One of the best experts on this subject based on the ideXlab platform.
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mechanism of potential profile formation in silicon Single Electron Transistors fabricated using pattern dependent oxidation
Japanese Journal of Applied Physics, 2001Co-Authors: Seiji Horiguchi, Yasuo Takahashi, Masao Nagase, Kenji Shiraishi, Hiroyuki Kageshima, Katsumi MuraseAbstract:The origin of the potential profile in silicon Single-Electron Transistors (SETs) fabricated using pattern-dependent oxidation (PADOX) is investigated by making use of the geometric structure measured by atomic force microscope (AFM), the bandgap reduction due to compressive stress generated during PADOX obtained using the first-principles calculation, and the effective potential method. A probable mechanism for the formation of the potential profile responsible for SET operation is proposed. The width reduction in the silicon wire region in the SET produces a tunnel barrier, while the compressive stress lowers the bottom of the conduction band through the bandgap reduction and forms a potential well corresponding to an island in the tunnel barrier.
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multigate Single Electron Transistors and their application to an exclusive or gate
Applied Physics Letters, 2000Co-Authors: Yasuo Takahashi, Kenji Yamazaki, Hideo Namatsu, Kenji Kurihara, Akira Fujiwara, Katsumi MuraseAbstract:The two-input exclusive-OR (XOR) function was implemented by a multigate Single-Electron transistor (SET). Two types of multigate SETs operating at 40 K were fabricated on a top silicon layer of an Si-on-insulator wafer by using a special technique called pattern-dependent oxidation. Two small gate electrodes which act as the input gates were formed over the small SET island. The output current of the devices took a high level when a high voltage was applied to either of the two gates with the other gate grounded, while it took a low level when both gates were grounded or fed with a high voltage. It is striking that such an XOR function can be implemented with just one device.
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fabrication method for ic oriented si Single Electron Transistors
IEEE Transactions on Electron Devices, 2000Co-Authors: Yukinori Ono, Yasuo Takahashi, Kenji Yamazaki, Masao Nagase, Hideo Namatsu, Kenji Kurihara, Katsumi MuraseAbstract:A new fabrication method for Si Single-Electron Transistors (SETs) is proposed. The method applies thermal oxidation to a Si wire with a fine trench across it on a silicon-on-insulator substrate. During the oxidation, the Si wire with the fine trench is converted, in a self-organized manner, into a twin SET structure with two Single-Electron islands, one along each edge of the trench, due to position-dependent oxidation-rate modulation caused by stress accumulation. Test devices demonstrated, at 40 K, that the twin SET structure can operate as two individual SET's. Since the present method produces two SET's at the same time in a tiny area, it is suitable for integrating logic circuits based on pass-transistor type logic and CMOS-type logic, which promises to lead to the fabrication of Single-Electron logic LSIs.
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suppression of effects of parasitic metal oxide semiconductor field effect Transistors on si Single Electron Transistors
Japanese Journal of Applied Physics, 1998Co-Authors: Akira Fujiwara, Yasuo Takahashi, Hideo Namatsu, Kenji Kurihara, Katsumi MuraseAbstract:Si Single-Electron Transistors (SETs), which are fabricated in ultrathin Si of a silicon-on-insulator substrate by pattern-dependent oxidation, are accompanied by parasitic metal-oxide-semiconductor field-effect Transistors (MOSFETs) on both sides of the SET. While the Si island of a SET is formed by design in a one-dimensional Si wire, the parasitic MOSFETs are inevitably formed in two-dimensional Si pad layers, between which the Si wire runs, because the poly-Si gate covers the Si pad layers as well as the Si island. Electrical characteristics of the device are strongly affected by these parasitic MOSFETs because of their relatively high resistance or the Coulomb blockade effect due to multiple islands unintentionally formed in the pad Si layers. We found that backgate voltage is useful for reducing or analyzing such parasitic effects. We propose a new fabrication technique; the use of a SiN mask for oxidation avoids unnecessary thinning of pad Si layers and parasitic effects can be suppressed.
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size dependence of the characteristics of si Single Electron Transistors on simox substrates
IEEE Transactions on Electron Devices, 1996Co-Authors: Yasuo Takahashi, Masao Nagase, Hideo Namatsu, Kenji Kurihara, K Iwadate, Katsumi MuraseAbstract:A Si Single-Electron transistor (SET) was fabricated by converting a one-dimensional (1-D) Si wire on a SIMOX substrate into a small Si island with a tunneling barrier at each end by means of pattern-dependent oxidation. Since the size of the Si island became as small as around 10 nm owing to this novel technique, the total capacitance of the SET was reduced to a value of the order of 1 aF, which guaranteed the conductance oscillation of the SET even at room temperature. Furthermore, a linear relation between the designed wire length and the gate capacitance of SET's was obtained, which clearly indicates that the Single island was actually formed in the middle of the one dimensional Si wire. These results were achieved owing to the highly reproducible fabrication process based on pattern dependent oxidation of SIMOX-Si layers.
Toshiro Hiramoto - One of the best experts on this subject based on the ideXlab platform.
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integrated circuits composed of nanowire and Single Electron Transistors operating at room temperature
IEEE Silicon Nanoelectronics Workshop, 2020Co-Authors: Tomoko Mizutani, Masaharu Kobayashi, Kiyoshi Takeuchi, Takuya Saraya, Toshiro HiramotoAbstract:Integrated circuits composed of nanowire Transistors and a silicon Single-Electron transistor on a chip have been fabricated. The circuit operations of current/voltage conversion and voltage amplification have been demonstrated at room temperature and at low operation voltage by nanowire MOS/SET circuits for the first time.
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experimental study on quantum confinement effects in silicon nanowire metal oxide semiconductor field effect Transistors and Single Electron Transistors
Journal of Applied Physics, 2008Co-Authors: Masaharu Kobayashi, Toshiro HiramotoAbstract:The effects of quantum confinement on transport properties of silicon nanowire metal-oxide-semiconductor field-effect Transistors (FETs) and Single-Electron Transistors are experimentally investigated. By carefully designing the channel width, the nanowire Transistors operate as silicon nanowire FETs (SNWFETs) or Single-charge Transistors. Large quantum confinement in ultranarrow silicon nanowires plays a key role in these devices. We also adopt a special device configuration in which both n-type and p-type operations can be attained in an identical device, and the dependence on the channel direction and charge polarity is intensively investigated. Statistical measurements and band structure calculation reveal that [110] p-channel SNWFETs show smaller threshold voltage variations and [100] Single-hole Transistors show the largest Coulomb blockade oscillations at room temperature.
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compact analytical model for room temperature operating silicon Single Electron Transistors with discrete quantum energy levels
IEEE Silicon Nanoelectronics Workshop, 2006Co-Authors: Kousuke Miyaji, Masumi Saitoh, Toshiro HiramotoAbstract:A compact and analytical model for silicon Single-Electron Transistors (SETs) considering the discrete quantum energy levels and the parabolic tunneling barriers is proposed. The model is based on a steady-state master equation that considers only the three most probable states derived from ground level and the first excited level for each number of Electrons in the dot to reduce the complexity while accounting for the quantum-level spacing and multiple peaks in Coulomb oscillation. Negative differential conductance (NDC) characteristics and aperiodic Coulomb oscillations due to nonuniform quantum-level spacings can be reproduced in this model. The model was compared with measurements, and good agreement was obtained. Simulations of some basic circuits that utilize NDC are successfully carried out by applying our model to the HSPICE circuit simulation. Our model can provide suitable environments for designing CMOS-combined room-temperature-operating highly functional SET circuits.
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control of coulomb blockade oscillations in silicon Single Electron Transistors using silicon nanocrystal floating gates
Applied Physics Letters, 2000Co-Authors: Nobuyoshi Takahashi, Hiroki Ishikuro, Toshiro HiramotoAbstract:We have fabricated Single-Electron Transistors (SETs) with Si nanocrystal floating gates, and experimentally demonstrated the control of the peak positions of Coulomb blockade oscillations. The positive voltage applied to the gate makes channel Electrons tunnel into the floating dots, and the injected Electrons raise the potential of quantum dots in SET, resulting in a shift of peak positions of Coulomb blockade oscillations. In addition, from the temperature dependence of device characteristics, it is confirmed that the potential fluctuations caused by random distribution of the Si nanocrystals have a slight influence on the shape of the Ids-Vg curves at practical high temperatures.
Yutaka Majima - One of the best experts on this subject based on the ideXlab platform.
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Memory operations in Au nanoparticle Single-Electron Transistors with floating gate electrodes
Applied Physics Letters, 2016Co-Authors: Yasuo Azuma, Masanori Sakamoto, Toshiharu Teranishi, Yutaka MajimaAbstract:Floating gate memory operations are demonstrated in a Single-Electron transistor (SET) fabricated by a chemical assembly using the Au nanogap electrodes and the chemisorbed Au nanoparticles. By applying pulse voltages to the control gate, phase shifts were clearly and stably observed both in the Coulomb oscillations and in the Coulomb diamonds. Writing and erasing operations on the floating gate memory were reproducibly observed, and the charges on the floating gate electrodes were maintained for at least 12 h. By considering the capacitance of the floating gate electrode, the number of Electrons in the floating gate electrode was estimated as 260. Owing to the stability of the fabricated SET, these writing and erasing operations on the floating gate memory can be applied to reconfigurable SET circuits fabricated by a chemically assembled technique.
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chemically assembled double dot Single Electron transistor analyzed by the orthodox model considering offset charge
Journal of Applied Physics, 2015Co-Authors: Shinya Kano, Masanori Sakamoto, Toshiharu Teranishi, Kosuke Maeda, Daisuke Tanaka, Yutaka MajimaAbstract:We present the analysis of chemically assembled double-dot Single-Electron Transistors using orthodox model considering offset charges. First, we fabricate chemically assembled Single-Electron Transistors (SETs) consisting of two Au nanoparticles between electroless Au-plated nanogap electrodes. Then, extraordinary stable Coulomb diamonds in the double-dot SETs are analyzed using the orthodox model, by considering offset charges on the respective quantum dots. We determine the equivalent circuit parameters from Coulomb diamonds and drain current vs. drain voltage curves of the SETs. The accuracies of the capacitances and offset charges on the quantum dots are within ±10%, and ±0.04e (where e is the elementary charge), respectively. The parameters can be explained by the geometrical structures of the SETs observed using scanning Electron microscopy images. Using this approach, we are able to understand the spatial characteristics of the double quantum dots, such as the relative distance from the gate electrode and the conditions for adsorption between the nanogap electrodes.
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control of charging energy in chemically assembled nanoparticle Single Electron Transistors
Nanotechnology, 2015Co-Authors: Yutaka Majima, Masanori Sakamoto, Toshiharu Teranishi, Shinya Kano, Daisuke TanakaAbstract:We show the control of a charging energy in chemically assembled nanoparticle Single-Electron Transistors (SETs) by altering the core diameter of Au nanoparticles. The charging energy is a fundamental parameter that decides the operating temperature of SETs. Practical application of SETs requires us to regulate the value of the charging energy by tuning the diameter of quantum dots. In this study, we used 3.0, 5.0 and 6.2 nm diameter synthesized Au nanoparticles as a quantum dot in the SETs. The total capacitances and charging energy of the SETs were evaluated from the rhombic Coulomb diamonds attributed to a Single Coulomb island. The capacitance and charging energy matched with a concentric sphere model much better than with a simple sphere model. The operating temperatures of the SETs suggested that a charging energy 2.2 times greater than the thermal energy was required for stable operation, in theory. These results will help us to select an appropriate core diameter for the Au nanoparticles in practical SETs.
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Ideal Discrete Energy Levels in Synthesized Au Nanoparticles for Chemically Assembled Single-Electron Transistors
ACS nano, 2012Co-Authors: Shinya Kano, Yasuo Azuma, Masanori Sakamoto, Toshiharu Teranishi, Kosuke Maeda, Daisuke Tanaka, L. W. Smith, Charles G. Smith, Yutaka MajimaAbstract:Ideal discrete energy levels in synthesized Au nanoparticles (6.2 ± 0.8 nm) for a chemically assembled Single-Electron transistor (SET) are demonstrated at 300 mK. The spatial structure of the double-gate SET is determined by two gate and drain voltages dependence of the stability diagram, and Electron transport to the Coulomb box of a Single, nearby Coulomb island of Au nanoparticles is detected by the SET. The SET exhibits discrete energy levels, and the excited energy level spacing of the Coulomb island is evaluated as 0.73 meV, which well corresponds to the expected theoretical value. The discrete energy levels show magnetic field evolution with the Zeeman effect and dependence on the odd–even Electron number of a Single Au nanoparticle.
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logic operations of chemically assembled Single Electron transistor
ACS Nano, 2012Co-Authors: Kosuke Maeda, Masanori Sakamoto, Toshiharu Teranishi, Shinya Kano, Daisuke Tanaka, Norio Okabayashi, Shuhei Takeshita, Yutaka MajimaAbstract:Double-gate Single-Electron Transistors (SETs) were fabricated by chemical assembling using electroless gold-plated nanogap electrodes and chemisorbed chemically synthesized gold nanoparticles. The fabricated SET showed periodic and stable Coulomb oscillations under application of voltages of both gates. The sole SET also exhibited all two-input logic operations—XOR, XNOR, NAND, OR, NOR, and AND—with an on/off ratio of 102. This demonstrates the potential of chemical assembling to give highly stable SETs exhibiting all logic operations.
Yasuo Takahashi - One of the best experts on this subject based on the ideXlab platform.
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binary adders of multigate Single Electron Transistors specific design using pass transistor logic
IEEE Transactions on Nanotechnology, 2002Co-Authors: Yukinori Ono, Hiroshi Inokawa, Yasuo TakahashiAbstract:We describe how to construct area-efficient adders using Single-Electron Transistors (SETs). The design is based on pass-transistor logic and multigate SETs are used as pass Transistors. The proposed design enables us to construct a full adder using only six SETs. We also show that multibit binary adders can be built using cascaded SET structures without any long wires. The small number of Transistors and no-metal-interconnection configuration significantly reduces the circuit area and capacitance to be charged. A Monte Carlo simulation shows that even when the inter-SET-node capacitances are reduced and consequently the carry signal level terribly fluctuates in its path due to Single-Electron charging effects, the carry can correctly propagate as long as the final output node capacitance is sufficiently large. This proves that the area reduction and speed improvement are compatible in our design. We also discuss the possibility of large-scale integration, touching on the random-offset-charge issue.
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mechanism of potential profile formation in silicon Single Electron Transistors fabricated using pattern dependent oxidation
Japanese Journal of Applied Physics, 2001Co-Authors: Seiji Horiguchi, Yasuo Takahashi, Masao Nagase, Kenji Shiraishi, Hiroyuki Kageshima, Katsumi MuraseAbstract:The origin of the potential profile in silicon Single-Electron Transistors (SETs) fabricated using pattern-dependent oxidation (PADOX) is investigated by making use of the geometric structure measured by atomic force microscope (AFM), the bandgap reduction due to compressive stress generated during PADOX obtained using the first-principles calculation, and the effective potential method. A probable mechanism for the formation of the potential profile responsible for SET operation is proposed. The width reduction in the silicon wire region in the SET produces a tunnel barrier, while the compressive stress lowers the bottom of the conduction band through the bandgap reduction and forms a potential well corresponding to an island in the tunnel barrier.
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multigate Single Electron Transistors and their application to an exclusive or gate
Applied Physics Letters, 2000Co-Authors: Yasuo Takahashi, Kenji Yamazaki, Hideo Namatsu, Kenji Kurihara, Akira Fujiwara, Katsumi MuraseAbstract:The two-input exclusive-OR (XOR) function was implemented by a multigate Single-Electron transistor (SET). Two types of multigate SETs operating at 40 K were fabricated on a top silicon layer of an Si-on-insulator wafer by using a special technique called pattern-dependent oxidation. Two small gate electrodes which act as the input gates were formed over the small SET island. The output current of the devices took a high level when a high voltage was applied to either of the two gates with the other gate grounded, while it took a low level when both gates were grounded or fed with a high voltage. It is striking that such an XOR function can be implemented with just one device.
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fabrication method for ic oriented si Single Electron Transistors
IEEE Transactions on Electron Devices, 2000Co-Authors: Yukinori Ono, Yasuo Takahashi, Kenji Yamazaki, Masao Nagase, Hideo Namatsu, Kenji Kurihara, Katsumi MuraseAbstract:A new fabrication method for Si Single-Electron Transistors (SETs) is proposed. The method applies thermal oxidation to a Si wire with a fine trench across it on a silicon-on-insulator substrate. During the oxidation, the Si wire with the fine trench is converted, in a self-organized manner, into a twin SET structure with two Single-Electron islands, one along each edge of the trench, due to position-dependent oxidation-rate modulation caused by stress accumulation. Test devices demonstrated, at 40 K, that the twin SET structure can operate as two individual SET's. Since the present method produces two SET's at the same time in a tiny area, it is suitable for integrating logic circuits based on pass-transistor type logic and CMOS-type logic, which promises to lead to the fabrication of Single-Electron logic LSIs.
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suppression of effects of parasitic metal oxide semiconductor field effect Transistors on si Single Electron Transistors
Japanese Journal of Applied Physics, 1998Co-Authors: Akira Fujiwara, Yasuo Takahashi, Hideo Namatsu, Kenji Kurihara, Katsumi MuraseAbstract:Si Single-Electron Transistors (SETs), which are fabricated in ultrathin Si of a silicon-on-insulator substrate by pattern-dependent oxidation, are accompanied by parasitic metal-oxide-semiconductor field-effect Transistors (MOSFETs) on both sides of the SET. While the Si island of a SET is formed by design in a one-dimensional Si wire, the parasitic MOSFETs are inevitably formed in two-dimensional Si pad layers, between which the Si wire runs, because the poly-Si gate covers the Si pad layers as well as the Si island. Electrical characteristics of the device are strongly affected by these parasitic MOSFETs because of their relatively high resistance or the Coulomb blockade effect due to multiple islands unintentionally formed in the pad Si layers. We found that backgate voltage is useful for reducing or analyzing such parasitic effects. We propose a new fabrication technique; the use of a SiN mask for oxidation avoids unnecessary thinning of pad Si layers and parasitic effects can be suppressed.
Kenji Kurihara - One of the best experts on this subject based on the ideXlab platform.
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multigate Single Electron Transistors and their application to an exclusive or gate
Applied Physics Letters, 2000Co-Authors: Yasuo Takahashi, Kenji Yamazaki, Hideo Namatsu, Kenji Kurihara, Akira Fujiwara, Katsumi MuraseAbstract:The two-input exclusive-OR (XOR) function was implemented by a multigate Single-Electron transistor (SET). Two types of multigate SETs operating at 40 K were fabricated on a top silicon layer of an Si-on-insulator wafer by using a special technique called pattern-dependent oxidation. Two small gate electrodes which act as the input gates were formed over the small SET island. The output current of the devices took a high level when a high voltage was applied to either of the two gates with the other gate grounded, while it took a low level when both gates were grounded or fed with a high voltage. It is striking that such an XOR function can be implemented with just one device.
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fabrication method for ic oriented si Single Electron Transistors
IEEE Transactions on Electron Devices, 2000Co-Authors: Yukinori Ono, Yasuo Takahashi, Kenji Yamazaki, Masao Nagase, Hideo Namatsu, Kenji Kurihara, Katsumi MuraseAbstract:A new fabrication method for Si Single-Electron Transistors (SETs) is proposed. The method applies thermal oxidation to a Si wire with a fine trench across it on a silicon-on-insulator substrate. During the oxidation, the Si wire with the fine trench is converted, in a self-organized manner, into a twin SET structure with two Single-Electron islands, one along each edge of the trench, due to position-dependent oxidation-rate modulation caused by stress accumulation. Test devices demonstrated, at 40 K, that the twin SET structure can operate as two individual SET's. Since the present method produces two SET's at the same time in a tiny area, it is suitable for integrating logic circuits based on pass-transistor type logic and CMOS-type logic, which promises to lead to the fabrication of Single-Electron logic LSIs.
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suppression of effects of parasitic metal oxide semiconductor field effect Transistors on si Single Electron Transistors
Japanese Journal of Applied Physics, 1998Co-Authors: Akira Fujiwara, Yasuo Takahashi, Hideo Namatsu, Kenji Kurihara, Katsumi MuraseAbstract:Si Single-Electron Transistors (SETs), which are fabricated in ultrathin Si of a silicon-on-insulator substrate by pattern-dependent oxidation, are accompanied by parasitic metal-oxide-semiconductor field-effect Transistors (MOSFETs) on both sides of the SET. While the Si island of a SET is formed by design in a one-dimensional Si wire, the parasitic MOSFETs are inevitably formed in two-dimensional Si pad layers, between which the Si wire runs, because the poly-Si gate covers the Si pad layers as well as the Si island. Electrical characteristics of the device are strongly affected by these parasitic MOSFETs because of their relatively high resistance or the Coulomb blockade effect due to multiple islands unintentionally formed in the pad Si layers. We found that backgate voltage is useful for reducing or analyzing such parasitic effects. We propose a new fabrication technique; the use of a SiN mask for oxidation avoids unnecessary thinning of pad Si layers and parasitic effects can be suppressed.
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size dependence of the characteristics of si Single Electron Transistors on simox substrates
IEEE Transactions on Electron Devices, 1996Co-Authors: Yasuo Takahashi, Masao Nagase, Hideo Namatsu, Kenji Kurihara, K Iwadate, Katsumi MuraseAbstract:A Si Single-Electron transistor (SET) was fabricated by converting a one-dimensional (1-D) Si wire on a SIMOX substrate into a small Si island with a tunneling barrier at each end by means of pattern-dependent oxidation. Since the size of the Si island became as small as around 10 nm owing to this novel technique, the total capacitance of the SET was reduced to a value of the order of 1 aF, which guaranteed the conductance oscillation of the SET even at room temperature. Furthermore, a linear relation between the designed wire length and the gate capacitance of SET's was obtained, which clearly indicates that the Single island was actually formed in the middle of the one dimensional Si wire. These results were achieved owing to the highly reproducible fabrication process based on pattern dependent oxidation of SIMOX-Si layers.