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C Y Khor - One of the best experts on this subject based on the ideXlab platform.
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influence of Solder Bump arrangements on molded ic encapsulation
Microelectronics Reliability, 2014Co-Authors: C Y Khor, M Z Abdullah, W C Leong, M Abdul S AzizAbstract:Abstract This paper presents a fluid–structure interaction (FSI) analysis of ball grid array (BGA) package encapsulation. Real-time and simultaneous FSI analysis is conducted by using finite volume code (FLUENT) and finite element code (ABAQUS), which are coupled with MpCCI. A BGA integrated circuit (IC) package with different Solder Bump arrangements is considered in this study. In the FSI analysis, effects of Solder Bump arrangements on pressure distribution, void, deformation, and stress imposed on the IC structures are investigated. The maximum deformation and maximum stress on the silicon chip and Solder Bumps are evaluated. The findings indicate that the full-array Solder Bump package encounters lower stress and deformation during encapsulation. The void formation of each Solder Bump arrangement is examined. Scaled-up encapsulation is performed and the predicted flow front advancements are substantiated by experimental results. Results demonstrate the excellent capability of the proposed modeling tools for predictive trends of IC encapsulation. Thus, better understanding of IC encapsulation is provided to engineers and package designers in the microelectronics industry.
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fluid structure interaction analysis of the effects of Solder Bump shapes and input output counts on moulded packaging
IEEE Transactions on Components Packaging and Manufacturing Technology, 2012Co-Authors: C Y Khor, M Z Abdullah, Wei Chiat LeongAbstract:This paper presents a fluid/structure interaction (FSI) analysis of the effects of Solder Bump shapes and input/output (I/O) counts on moulded packaging. The FSI events during the encapsulation process are investigated using a virtual modeling technique, whose mesh-based parallel code-coupling interface couples both finite volume and finite element codes. In this paper, the effects of five different Solder Bump shapes, denoted Cases 1-5, are considered in the perimeter and full array of Solder Bump arrangements with different I/O counts. The FSI between the epoxy moulding compound and structures (silicon chip and Solder Bumps) is presented in the displacement profile. The effects of the Bump shape and I/O count are considered in the flow front advancement, structure displacement, stress, and void formation. The maximum displacements, von Mises stresses, and voids are minimized by implementing the Bump shape in Case 3. The applications of Cases 3 and 5 with higher I/O counts (full array type) reduced the stress concentration in the Solder Bump by nearly 40% and 60%, respectively, compared to the cases with lower I/O counts (perimeter type).
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fvm based numerical study on the effect of Solder Bump arrangement on capillary driven flip chip underfill process
International Communications in Heat and Mass Transfer, 2010Co-Authors: C Y Khor, M Z Abdullah, Abdul M MujeebuAbstract:In this paper, the finite volume method (FVM) based numerical simulation is used for the flow visualization of capillary driven underfill process for different Solder Bump arrangements of flip chip packages is presented. Three different 3D flip chip package models are developed and simulated using computational fluid dynamic (CFD) code, FLUENT 6.3. Capillary action and cross viscosity model are taken into account in the simulation. One-line dispensing method is applied in the analysis and the volume of fluid (VOF) technique is used to track the flow front. The effect of Solder balls arrangement on flow behavior and filling time is studied and the Solder balls arrangement is found to affect the flow behavior and filling time. The flow patterns of simulation are observed for three flip chip packages and compared. The ability of the proposed model and FLUENT in handling flip chip underfill problems is proved to be excellent.
Kyungwook Paik - One of the best experts on this subject based on the ideXlab platform.
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Effects of the Curing Properties and Viscosities of Non-Conductive Films (NCFs) on the Sn-Ag Solder Bump Joint Morphology and Reliability
2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019Co-Authors: Sangmyung Shin, Taejin Choi, Sooin Park, Kyungwook PaikAbstract:In this study, Solder Bump flip chip assembly using NCFs was evaluated for Sn-Ag Solder Bumps. Flip chip bonding was performed using an isothermal Thermo-Compression (TC) bonding method for 5 seconds. Solder Bump joints were evaluated by adjusting the curing properties such as curing onset, peak temperature, and degree of curing and viscosities of NCFs using curing agents and silica contents. And then, the degree of cure and viscosity approximations were conducted to define the precise viscosity of NCFs at the Solder melting temperature using measured degree of cures at various bonding temperatures and viscosities. Finally, high temperature and humidity test (85RH%/85°C test) and temperature cycling (T/C) test were performed to evaluate the thermo-mechanical reliability performance depending on Solder joint.
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A Study on the Curing Properties and Viscosities of Non-Conductive Films (NCFs) for Sn-Ag Solder Bump Flip Chip Assembly
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018Co-Authors: Jongho Park, Chang-kyu Chung, Kyung-woon Jang, Seongwoo Choi, Kyungwook PaikAbstract:In this study, flip chip assembly using NCFs was evaluated in Sn-Ag Solder Bump structure. Thermo-Compression (TC) flip chip bonding was performed within 5 seconds using an isothermal TC bonding method. Solder joint morphology was evaluated by adjusting curing properties of NCFs such as curing onset and peak temperature and degree of curing and also viscosities, and the best NCFs properties were optimized. In addition, bonding process conditions were also optimized in terms of Solder gap heights and daisy chain electrical resistances. Finally, 85°C/85RH% test and temperature cycling (T/C) reliability test were performed to evaluate the thermo-mechanical and hygroscopic reliability performance of Solder joint using NCFs.
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A study on the intermetallic growth of fine-pitch Cu pillar/SnAg Solder Bump for 3D-TSV interconnection
2012 IEEE 62nd Electronic Components and Technology Conference, 2012Co-Authors: Yong-sung Park, Ji-won Shin, Yong-won Choi, Kyungwook PaikAbstract:The IMC growth of fine pitch Cu pillar/SnAg Solder Bumps used for the chip to chip eutectic bonding of 3D-TSV interconnection was investigated. Most of SnAg Solder was rapidly consumed by Cu-Sn intermetallic compound (IMC) growth during the eutectic bonding process. The composition of the IMC phase were identified as Cu-Au-Sn ternary phase and the main TEM diffraction patterns were well matched with the Cu6Sn5 crystal structure and the two week diffraction spots between every two strong spots matched with the superlattice of Au atoms. As a result, it was proved that the Cu-Au-Sn ternary IMCs were (Cu, Au)6Sn5. In the case of a large Solder joint such as BGA (Ball Grid Array) or CSP (Chip Scale Package), most of the Au deposited on a metal pad was dissolved in the melting Solder region due to relatively little Au content. However, in the case of TSV Cu pillar/SnAg Solder Bump jointed on the Au coated Cu pad, Au atoms were completely dissolved in the Solder and participated in the IMC reaction due to the very small amount of Solder.
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electromigration in flip chip Solder Bump of 97pb 3sn 37pb 63sn combination structure
Acta Materialia, 2004Co-Authors: Kyungwook PaikAbstract:Abstract Electromigration damage in the flip chip Solder Bump of 97Pb–3Sn/37Pb–63Sn (numbers are all in wt% unless specified otherwise) combination structure was studied after current stressing at 140 °C with a density of 2.55 × 10 4 A/cm 2 for up to 20 h. The under Bump metallurgy for the 97Pb–3Sn Solder on the chip side was TiW/Cu/electroplated Cu while the bond-pad for the 37Pb–63Sn Solder on the printed circuit board (PCB) side was electroless Ni/Au. We observed in the thermo-electromigration test that failure occurred at the top of the Bump with a downward electrical current flow while there was no failure in the opposite current polarity. The Pb atoms were found to move in the same direction as with the electron current flow. Therefore, in the case of the downward electron flow, the composition of the upper Solder Bump changed from 97Pb–3Sn to 83Pb–17Sn and it enabled the Cu 6 Sn 5 phase to precipitate onto the chip side. Due to the precipitation and growth of the Cu 6 Sn 5 intermetallic compound, the Cu under Bump metallurgy was quickly consumed and the subsequent void formation induced failure.
M Z Abdullah - One of the best experts on this subject based on the ideXlab platform.
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influence of Solder Bump arrangements on molded ic encapsulation
Microelectronics Reliability, 2014Co-Authors: C Y Khor, M Z Abdullah, W C Leong, M Abdul S AzizAbstract:Abstract This paper presents a fluid–structure interaction (FSI) analysis of ball grid array (BGA) package encapsulation. Real-time and simultaneous FSI analysis is conducted by using finite volume code (FLUENT) and finite element code (ABAQUS), which are coupled with MpCCI. A BGA integrated circuit (IC) package with different Solder Bump arrangements is considered in this study. In the FSI analysis, effects of Solder Bump arrangements on pressure distribution, void, deformation, and stress imposed on the IC structures are investigated. The maximum deformation and maximum stress on the silicon chip and Solder Bumps are evaluated. The findings indicate that the full-array Solder Bump package encounters lower stress and deformation during encapsulation. The void formation of each Solder Bump arrangement is examined. Scaled-up encapsulation is performed and the predicted flow front advancements are substantiated by experimental results. Results demonstrate the excellent capability of the proposed modeling tools for predictive trends of IC encapsulation. Thus, better understanding of IC encapsulation is provided to engineers and package designers in the microelectronics industry.
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fluid structure interaction analysis of the effects of Solder Bump shapes and input output counts on moulded packaging
IEEE Transactions on Components Packaging and Manufacturing Technology, 2012Co-Authors: C Y Khor, M Z Abdullah, Wei Chiat LeongAbstract:This paper presents a fluid/structure interaction (FSI) analysis of the effects of Solder Bump shapes and input/output (I/O) counts on moulded packaging. The FSI events during the encapsulation process are investigated using a virtual modeling technique, whose mesh-based parallel code-coupling interface couples both finite volume and finite element codes. In this paper, the effects of five different Solder Bump shapes, denoted Cases 1-5, are considered in the perimeter and full array of Solder Bump arrangements with different I/O counts. The FSI between the epoxy moulding compound and structures (silicon chip and Solder Bumps) is presented in the displacement profile. The effects of the Bump shape and I/O count are considered in the flow front advancement, structure displacement, stress, and void formation. The maximum displacements, von Mises stresses, and voids are minimized by implementing the Bump shape in Case 3. The applications of Cases 3 and 5 with higher I/O counts (full array type) reduced the stress concentration in the Solder Bump by nearly 40% and 60%, respectively, compared to the cases with lower I/O counts (perimeter type).
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fvm based numerical study on the effect of Solder Bump arrangement on capillary driven flip chip underfill process
International Communications in Heat and Mass Transfer, 2010Co-Authors: C Y Khor, M Z Abdullah, Abdul M MujeebuAbstract:In this paper, the finite volume method (FVM) based numerical simulation is used for the flow visualization of capillary driven underfill process for different Solder Bump arrangements of flip chip packages is presented. Three different 3D flip chip package models are developed and simulated using computational fluid dynamic (CFD) code, FLUENT 6.3. Capillary action and cross viscosity model are taken into account in the simulation. One-line dispensing method is applied in the analysis and the volume of fluid (VOF) technique is used to track the flow front. The effect of Solder balls arrangement on flow behavior and filling time is studied and the Solder balls arrangement is found to affect the flow behavior and filling time. The flow patterns of simulation are observed for three flip chip packages and compared. The ability of the proposed model and FLUENT in handling flip chip underfill problems is proved to be excellent.
Abdul M Mujeebu - One of the best experts on this subject based on the ideXlab platform.
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fvm based numerical study on the effect of Solder Bump arrangement on capillary driven flip chip underfill process
International Communications in Heat and Mass Transfer, 2010Co-Authors: C Y Khor, M Z Abdullah, Abdul M MujeebuAbstract:In this paper, the finite volume method (FVM) based numerical simulation is used for the flow visualization of capillary driven underfill process for different Solder Bump arrangements of flip chip packages is presented. Three different 3D flip chip package models are developed and simulated using computational fluid dynamic (CFD) code, FLUENT 6.3. Capillary action and cross viscosity model are taken into account in the simulation. One-line dispensing method is applied in the analysis and the volume of fluid (VOF) technique is used to track the flow front. The effect of Solder balls arrangement on flow behavior and filling time is studied and the Solder balls arrangement is found to affect the flow behavior and filling time. The flow patterns of simulation are observed for three flip chip packages and compared. The ability of the proposed model and FLUENT in handling flip chip underfill problems is proved to be excellent.
Hirokazu Ezawa - One of the best experts on this subject based on the ideXlab platform.
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Low-stress interconnection for flip chip BGA employing lead-free Solder Bump
Proceedings - Electronic Components and Technology Conference, 2007Co-Authors: Masayuki Uchida, Hisashi Ito, Hideo Nishiuchi, Takashi Togasaki, Ken Yabui, Kazuhito Higuchi, Hirokazu EzawaAbstract:Flip chip bonding technology has been widely used for interconnection in high-end logic LSI employing lead-rich Solder Bumps. Recently, from an environmental issue, it is desired that the lead-rich Solder should be replaced by lead-free Solder. However, the stress at the interconnection after flip chip bonding reflow cannot be relaxed with lead-free Solder Bumps because of their poor creep properties. Since the stress causes delamination of the low-k layer under Bumps and electrical open errors, the improvement of the Solder Bump material and the flip chip bonding process have been necessary for stress relaxation. In this study, we investigated the creep properties of Sn-0.7Cu and Sn-3.5Ag Bumps by the indentation method. As a result, it was found that the creep properties of Sn-0.7Cu Bumps was more suitable for stress relaxation than those of Sn-3.5Ag. Moreover, we confirmed that a low-stress interconnection had been achieved by employing Sn-0.7Cu Bumps. The stress at the interconnection was less than the delaminating stress of the low-k layer. In addition, when the flip chip bonding was carried out by the reflow with the post-annealing, in which the temperature was held for a period of time at 200degC during reflow cooling part, the maximum stress in the low-k layer has been reduced by more than 36% in comparison with the low-k delaminating stress. Furthermore, it was found that the stresses at the flip chip joints were relaxed because of the increase of the creep rate which was caused by the reflow with the post-annealing.
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Eutectic Sn-Ag Solder Bump process for ULSI flip chip technology
IEEE Transactions on Electronics Packaging Manufacturing, 2001Co-Authors: Hirokazu Ezawa, M. Miyata, S. Honma, H. Inoue, T. Tokuoka, J. Yoshioka, M. TsujimuraAbstract:A novel eutectic Pb-free Solder Bump process, which provides several advantages over conventional Solder Bump process schemes, has been developed. A thick plating mask can be fabricated for steep wall Bumps using a nega-type resist with a thickness of more than 50 /spl mu/m by single-step spin coating. This improves productivity for mass production. The two-step electroplating is performed using two separate plating reactors for Ag and Sn. The Sn layer is electroplated on the Ag layer. Eutectic Sn-Ag alloy Bumps can be easily obtained by annealing the Ag/Sn metal stack. This electroplating process does not need strict control of the Ag to Sn content ratio in alloy plating solutions. The uniformity of the reflowed Bump height within a 6-in wafer was less than 10%. The Ag composition range within a 6-in wafer was less than /spl plusmn/0.3 wt.% Ag at the eutectic Sn-Ag alloy, analyzed by ICP spectrometry. SEM observations of the Cu/barrier layer/Sn-Ag Solder interface and shear strength measurements of the Solder Bumps were performed after 5 times reflow at 260/spl deg/C in N/sub 2/ ambient. For the Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier layer, the shear strength decreased to 70% due to the formation of Sn-Cu intermetallic compounds. Thicker Ti in the barrier metal stack improved the shear strength. The thermal stability of the Cu/barrier layer/Sn-Ag Solder metal stack was examined using Auger electron spectrometry analysis. After annealing at 150/spl deg/C for 1000 h in N/sub 2/ ambient, Sn did not diffuse into the Cu layer for Ti(500 nm)/Ni(300 nm)/Pd(50 nm) and Nb(360 nm)/Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier metal stacks. These results suggest that the Ti/Ni/Pd barrier metal stack available to Sn-Pb Solder Bumps and Au Bumps on Al pads is viable for Sn-Ag Solder Bumps on Cu pads in upcoming ULSIs.
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Eutectic Sn-Ag Solder Bump process for ULSI flip chip technology
2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070), 2000Co-Authors: Hirokazu Ezawa, M. Miyata, S. Honma, H. Inoue, T. Tokuoka, J. Yoshioka, M. TsujimuraAbstract:The novel developed Sn-Ag eutectic Solder Bump process provides several advantages over conventional Solder Bump process schemes. Steep wall Bumps as plated were fabricated using the nega-type photo resist with a thickness of more than 50 /spl mu/m by one time spin coating. This improves productivity for mass production. The 2-step electroplating process was performed using separate plating reactors for Ag and Sn. The eutectic Sn-Ag alloy Bumps were easily obtained by annealing the metal stacks with Sn layer on Ag layer sequentially electroplated. This electroplating process does not need to strict control of the content ratio of Ag to Sn in an alloy plating solution even with increasing electroplating depositions. The novel developed process gives the within-wafer uniformity of the Bump height as reflowed of less than 10% and of the Sn-Ag alloy composition as reflowed of less than /spl plusmn/0.5wt.%Ag, analyzed by ICP spectrometry. Shear strength measurements were performed to known thermal stability for the structure of Cu pads/Ti/Ni/Pd/Sn-Ag eutectic Solder stack. In the case of the Ti (100 nm)/Ni (300 nm)/Pd (50 nm) barrier metal stacks, the shear strength after 5 times annealing in N2 ambience at 260/spl deg/C decreased to 70% than that as reflowed. As the Ti becomes thicker in the Ti/Ni/Pd metal stack, shear strengths are improved. Comparing the structure of Cu/Ti/Ni/Pd/Sn-Ag eutectic Solder with the case of Ta/Ti/Ni/Pd and Nb/Ti/Ni/Pd barrier metal stacks. The analysis results of Auger spectrometry show that Sn diffusion into Cu to form Cu-Sn alloy was observed only in Cu/Ta/Ti/Ni/Pd barrier metal stacks. These results suggest that the same Ti/Ni/Pd barrier metal stack as used in Sn-Pb Solder Bump and Au Bump is viable for ULSIs with Cu interconnects.
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Eutectic Solder Bump process for ULSI flip chip technology
Twenty First IEEE CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium, 1997Co-Authors: Hirokazu Ezawa, M. Miyata, H. InoueAbstract:A novel eutectic Solder Bump process, which allows ULSI chips area array pad layout, has been developed. Straight side wall Bumps as plated using a new negative-type photoresist and eutectic Solder electroplating provide several advantages over conventional mushroom Bumps. The novel developed process gives the Bump height uniformity as reflowed of less than 10% within the wafer. Composition measurements using ICP spectrometry have been performed to investigate the Bump height dependence on Solder compositions and the metal content dependence of a plating solution on the Solder composition uniformity within the wafer. Experimental results show that the plating solution with the total metal concentration of more than 60 g/l gives a uniformity at eutectic point of less than 3% within wafer. In addition, we have confirmed that the use of a eutectic Solder disk anode keeps the composition of a plating solution constant for a long term product run.