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Ken Takeuchi - One of the best experts on this subject based on the ideXlab platform.
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3d nand flash solid state drive ssd for deep neural network weight storage of iot edge devices with 700x data retention lifetime extention
International Memory Workshop, 2018Co-Authors: Yoshiaki Deguchi, Ken TakeuchiAbstract:3D-TLC (triple-level cell) NAND flash-based solid-state drive (SSD) for deep neural network (DNN) weight storage is proposed. The data-retention lifetime of 3D-TLC NAND flash memory is extended by 700-times to achieve over 10-year lifetime of IoT edge devices such as automobiles and infrastructures. Proposed SSD combines reliability enhancement techniques for 3D-TLC NAND flash memories with unique characteristics of DNN weights, which have values of near 0. This paper proposes two techniques for SSD controller. The 1st proposal, One-state Error Recovery, removes all of 1-state errors of important bits in DNN weights even when error-correcting code (ECC) cannot correct errors. The 2nd proposal, DNN Weight Data Mapping, assigns frequently used "0" to the highly reliable VTH-state of memory cells. Due to error tolerance of DNN weights, acceptable bit error rate (BER) increases by 9.8-times.
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0 6 v operation 16 faster set reset reram boost converter with adaptive buffer voltage for reram and nand flash hybrid solid state drives
International Symposium on Quality Electronic Design, 2017Co-Authors: Kota Tsurumi, Masahiro Tanaka, Ken TakeuchiAbstract:A 0.6 V boost converter with adaptive buffer voltage is proposed for 3D-integrated Random Access Memory (ReRAM) and NAND flash memory hybrid solid-state drive (SSD). The proposed boost converter with 1- or 2-stage charge pump has two advantages by changing buffer voltage depending on program data size. First, the proposed boost converter with 2-stage charge pump (proposed circuit) decreases SET/RESET time of ReRAM by 97 % compared with the conventional boost converter with no charge pump (conventional 1) [1]. Second, compared with the conventional boost converter with 1-stage charge pump (conventional 2) [2], the total program time is decreased by 16 % with the proposed circuit when the program data size is as large as 10 sectors (5 kbyte). The boost converter and the charge pump are fabricated with the 180 nm standard CMOS process.
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optimal memory configuration analysis in tri hybrid solid state drives with storage class memory and multi level cell triple level cell nand flash memory
Japanese Journal of Applied Physics, 2017Co-Authors: Tomoaki Yamada, Yusuke Sugiyama, Yusuke Yamaga, Ken TakeuchiAbstract:This paper analyzes the best mix of memories in a tri-hybrid solid-state drive (SSD) with storage class memory (SCM) and multi-level cell (MLC)/triple-level cell (TLC) NAND flash memory. SCM is fast but its cost is high. Although MLC NAND flash memory is slow, it is more cost effective than SCM. For further cost efficiency, TLC NAND flash memory is denser and less expensive than MLC NAND flash. Performance of tri-hybrid SSD is evaluated in various memory configurations. Moreover, the optimum memory configuration is changed according to the application characteristics. If 10% cost increase is allowed compared to the MLC NAND flash only SSD, SCM/MLC NAND flash hybrid SSD provides the best performance with hot/random workload, whereas SCM/MLC/TLC NAND flash tri-hybrid SSD achieves the best for hot/sequential and cold/random workloads. In addition, it is possible to add long latency but low-cost SCM to the tri-hybrid SSD. As a result, tri-hybrid SSD with slow SCM achieves the best performance.
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design guidelines of storage class memory flash hybrid solid state drive considering system architecture algorithm and workload characteristic
IEEE Transactions on Consumer Electronics, 2016Co-Authors: Shun Okamoto, Tomoaki Yamada, Shogo Hachiya, Ken TakeuchiAbstract:solid-state drives (SSDs), composed of NAND flash memories, are replacing hard disk drives (HDDs) rapidly. In addition, storage class memories (SCMs) bridge the bandwidth gap between DRAM and NAND flash, thus introducing SCM to SSD further improves the solid storage performance. Different from schemes that use SCM to store file system metadata or logical to physical mapping tables, two architectures 1) use SCM as a write-back non-volatile memory (NVM) based cache, 2) use SCM as a storage device are presented in this paper. Since SCM chip latency varies due to memory device and circuit design, three SSD data management algorithms are evaluated under five SCM chip design scenarios to provide useful design guidelines of SCM/NAND flash hybrid SSD. SCM interface and capacity requirement are also analyzed. From the experimental results, less than 10% of the SCM/NAND flash capacity ratio is enough for SCM chips with 500 ns read and 5 μs write latency to boost NAND flash-only SSD speed by over 10 times when workloads own high IO skew1.
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0 6 1 0 v operation set reset voltage 3 v generator for three dimensional integrated resistive random access memory and nand flash hybrid solid state drive
Japanese Journal of Applied Physics, 2016Co-Authors: Masahiro Tanaka, Shogo Hachiya, Tomoya Ishii, Sheyang Ning, Kota Tsurumi, Ken TakeuchiAbstract:A 0.6–1.0 V, 25.9 mm2 boost converter is proposed to generate resistive random access memory (ReRAM) write (set/reset) voltage for three-dimensional (3D) integrated ReRAM and NAND flash hybrid solid-state drive (SSD). The proposed boost converter uses an integrated area-efficient V BUF generation circuit to obtain short ReRAM sector write time, small circuit size, and small energy consumption simultaneously. In specific, the proposed boost converter reduces ReRAM sector write time by 65% compared with a conventional one-stage boost converter (Conventional 1) which uses 1.0 V operating voltage. On the other hand, by using the same ReRAM sector write time, the proposed boost converter reduces 49% circuit area and 46% energy consumption compared with a conventional two-stage boost converter (Conventional 2). In addition, by using the proposed boost converter, the operating voltage, V DD, can be reduced to 0.6 V. The lowest 159 nJ energy consumption can be obtained when V DD is 0.7 V.
Shuhei Tanakamaru - One of the best experts on this subject based on the ideXlab platform.
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highly reliable and low power ssd using asymmetric coding and stripe bitline pattern elimination programming
IEEE Journal of Solid-state Circuits, 2012Co-Authors: Shuhei Tanakamaru, C Hung, Kai TakeuchiAbstract:Highly reliable and low power solid-state drive (SSD) is proposed. Through the analysis based on measured error rate in the SSDs with NAND flash memories, the memory cell error shows the asymmetric characteristic in multilevel cell (MLC) NAND flash memories. The proposed asymmetric coding increases the number of “1” s or “0” s of the programming data to reduce the data retention error. The numbers of the memory cells in the higher VTH states are reduced. The memory cell error is reduced by 90% with the asymmetric coding. On the other hand, the inter bit-line capacitance significantly increases with the scaling of memory cells. The bit-line charging current becomes unacceptably large. To decrease the write power consumption, the stripe pattern elimination algorithm (SPEA) is proposed. The SPEA eliminates the column-stripe pattern which consumes the maximum power to charge all of the inter bit-line capacitance in a NAND chip. Theoretical analyses are given for both the asymmetric coding and the SPEA. The asymmetric coding and the SPEA can be used together with the other highly reliable or low power techniques such as intelligent interleaving and adaptive code selection scheme and realizes the high reliability and low power consumption.
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95 lower ber 43 lower power intelligent solid state drive ssd with asymmetric coding and stripe pattern elimination algorithm
International Solid-State Circuits Conference, 2011Co-Authors: Shuhei Tanakamaru, Chinglin Hung, Atsushi Esumi, Kai Li, Ken TakeuchiAbstract:This paper presents intelligent solid-state drives (SSDs), which decrease memory errors by 95% and reduce power consumption by 43%. Figure 11.4.1 shows the measured memory cell error in the data retention and program disturb of 4X, 3X and 2Xnm NAND flash memories. As the memory size decreases, both data retention and program disturb errors increase due to the interference, random telegraph noise and reduced electrons [1]. In the scaled NAND, the electric field in the channel increases [2] and the program disturb due to GIDL-induced hot electron injection becomes more significant (Fig. 11.4.1(c)). In conventional SSDs, 20 to 40b correction per 1KB codeword error-correcting code (ECC) is used to correct errors [3]. As stronger codes, such as LDPC, are developed [4], the capability of ECC is close to the Shannon limit of a few percent error correction. Thus, the additional high-reliability scheme is required. As the feature size decreases, the power consumption increases due to the increased bit-line capacitance of NAND [5]. As the space between bitlines decreases, the inter bitline capacitance increases. To overcome reliability and power problems in SSDs, this paper describes two technologies. Asymmetric coding improves memory-cell reliability by 95% without access-time penalty. Stripe pattern elimination algorithm eliminates the worst program data pattern and decreases the power during the program by 43% without circuit area or access time overhead.
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95 lower ber 43 lower power intelligent solid state drive ssd with asymmetric coding and stripe pattern elimination algorithm
International Solid-State Circuits Conference, 2011Co-Authors: Shuhei Tanakamaru, Chinglin Hung, Atsushi Esumi, Mitsuyoshi Ito, Ken TakeuchiAbstract:This paper presents intelligent solid-state drives (SSDs), which decrease memory errors by 95% and reduce power consumption by 43%. Figure 11.4.1 shows the measured memory cell error in the data retention and program disturb of 4X, 3X and 2Xnm NAND flash memories. As the memory size decreases, both data retention and program disturb errors increase due to the interference, random telegraph noise and reduced electrons [1]. In the scaled NAND, the electric field in the channel increases [2] and the program disturb due to GIDL-induced hot electron injection becomes more significant (Fig. 11.4.1(c)). In conventional SSDs, 20 to 40b correction per 1KB codeword error-correcting code (ECC) is used to correct errors [3]. As stronger codes, such as LDPC, are developed [4], the capability of ECC is close to the Shannon limit of a few percent error correction. Thus, the additional high-reliability scheme is required. As the feature size decreases, the power consumption increases due to the increased bit-line capacitance of NAND [5]. As the space between bitlines decreases, the inter bitline capacitance increases. To overcome reliability and power problems in SSDs, this paper describes two technologies. Asymmetric coding improves memory-cell reliability by 95% without access-time penalty. Stripe pattern elimination algorithm eliminates the worst program data pattern and decreases the power during the program by 43% without circuit area or access time overhead.
Michael Cornwell - One of the best experts on this subject based on the ideXlab platform.
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anatomy of a solid state drive
Communications of The ACM, 2012Co-Authors: Michael CornwellAbstract:While the ubiquitous SSD shares many features with the hard-disk drive, under the surface they are completely different.
Luca Perniola - One of the best experts on this subject based on the ideXlab platform.
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phase change and magnetic memories for solid state drive applications
Proceedings of the IEEE, 2017Co-Authors: Cristian Zambelli, Gabriele Navarro, V Sousa, Ioan Lucian Prejbeanu, Luca PerniolaAbstract:The state-of-the-art solid-state drives (SSDs) now heterogeneously integrate NAND Flash and dynamic random access memories (DRAMs) to partially hide the limitation of the nonvolatile memory technology. However, due to the increased request for storage density coupled with performance that positions the storage tier closer to the latency of the processing elements, NAND Flash are becoming a serious bottleneck. DRAM as well are a limitation in the SSD reliability due to their vulnerability to the power loss events. Several emerging memory technologies are candidate to replace them, namely the storage class memories. Phase change memories and magnetic memories fall into this category. In this work, we review both technologies from the perspective of their possible application in future disk drives, opening up new computation paradigms as well as improving the storage characteristics in terms of latency and reliability.
Takayasu Sakurai - One of the best experts on this subject based on the ideXlab platform.
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Through-silicon via design for a 3-D solid-state drive system with boost converter in a package
IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011Co-Authors: Koh Johguchi, Teruyoshi Hatanaka, Tadashi Yasufuku, Makoto Takamiya, Koichi Ishida, Takayasu SakuraiAbstract:A 3-D solid-state drive system with through-silicon via (TSV) technology\nand boost converter is presented in this paper. The proposed boost\nconverter enables the supply voltage reduction to 1.8 V and smaller NAND\nFlash memory chips. From the simulation results, the conventional\nbonding-wire technology can achieve only eight NAND chip integrations\nnot only due to their structural problem but also due to the performance\ndegradation. On the other hand, 128 NAND Flash memory chips can be\nintegrated into a package with full-copper TSVs and the proposed system\nhas about 1.70 mu s of rise time for 20 V, 74.2 nJ of the energy\ndissipation, and 225 mu m(2) of additional Si area consumption for a\nNAND chip. Even if poly-Si TSVs are used, because of the process\nrestriction, 64 NAND chips can be stacked with about 34% longer rise\ntime and 22% degradation of energy dissipation compared to a\nfull-copper TSV by grinding the Si-substrate to 10 mu m.
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Inductor and TSV Design of 20-V Boost Converter for Low Power 3D solid state drive with NAND Flash Memories
IEICE TRANSACTIONS ON ELECTRONICS, 2010Co-Authors: Tadashi Yasufuku, Hiroto Nakai, Makoto Takamiya, Shinji Miyamoto, Koichi Ishida, Takayasu SakuraiAbstract:Two essential technologies for a 3D solid state drive (3D-SSD) with a\nboost convener are presented in this paper The first topic is the spiral\ninductor design which determines the performance of the boost converter,\nand the second is the effect of TSV's on the boost converter These\ntechniques are very important in achieving a 3D-SSD with a boost\nconverter In the design of the inductor, the on-board inductor from 250\nto 320 nH Is the best design feature that meets all requriements,\nincluding high output voltage above 20 V. fast rise lime, low energy\nconsumption. and area smaller than 25 mm(2) The use of a boost converter\nwith the proposed inductor leads to a reduction of the energy\nconsumption during the write operation of the proposed 1 8-V 3D-SSD by\n68% compared with the conventional 3 3-V 3D-SSD with the charge pump\nThe feasibility of 3D-SSD's with Through Silicon Vias (TSV's)\nconnections is also discussed In order to maintain the advantages of the\nboost converter over the charge pump. the reduction of the parasitic\nresistance of TSV's is very important
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effect of resistance of tsv s on performance of boost converter for low power 3d ssd with nand flash memories
2009 IEEE International Conference on 3D System Integration, 2009Co-Authors: Tadashi Yasufuku, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Shinji Miyamoto, Koichi Ishida, Ken TakeuchiAbstract:This paper investigates the effect of the TSV resistance (R TSV ) on the performance of boost converters for solid state drive (SSD) using circuit simulation. When R TSV is 0Ω, both the rising time (t rise ) from 0V to 15V and the energy during boosting (E loss ) of the output voltage (V OUT ) are 10.6% and 6.6% of the conventional charge pump respectively. In contrast, when R TSV is 200O, for example, t rise is 30.1% and E loss is 22.8% of the conventional charge pump. Besides, V OUT cannot be boosted above 20V when R TSV is larger than 210Ω. Therefore, in order to maintain the advantages of the boost converter over the charge pump in terms of t rise and E loss , the reduction of R TSV is very important.
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inductor design of 20 v boost converter for low power 3d solid state drive with nand flash memories
International Symposium on Low Power Electronics and Design, 2009Co-Authors: Tadashi Yasufuku, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Shinji Miyamoto, Koichi Ishida, Ken TakeuchiAbstract:A 3D-integrated solid state drive (SSD) with the boost converter can achieve both the low power and the fast write-operation at the small die area of the NAND flash memory. The performance of the boost converter, however, is critically affected by the inductor, because the output voltage of the boost converter, the rising time, and the energy consumption during the boost are determined by the inductor. Therefore, this paper proposes a design methodology of the inductor of the boost converter for the 3D SSD. By using the boost converter with the optimized inductor, the energy during write-operation of the proposed 1.8-V 3D-SSD is decreased by 68% compared with the conventional 3.3-V 3D-SSD with the charge pump.