The Experts below are selected from a list of 252 Experts worldwide ranked by ideXlab platform
Yiu-fai Chan - One of the best experts on this subject based on the ideXlab platform.
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a portable digital dll for high Speed cmos Interface circuits
IEEE Journal of Solid-state Circuits, 1999Co-Authors: Bruno W Garlepp, Kevin S Donnelly, Jun Kim, Jared L Zerbe, C Huang, Chanh Tran, Clemenz Portmann, D Stark, Park Chau, Yiu-fai ChanAbstract:A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-Speed Interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.
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a portable digital dll architecture for cmos Interface circuits
Symposium on VLSI Circuits, 1998Co-Authors: Bruno W Garlepp, Kevin S Donnelly, Jun Kim, Pak Shing Chau, Jared L Zerbe, C Huang, Chanh Tran, Clemenz Portmann, D Stark, Yiu-fai ChanAbstract:A digital DLL was developed which achieves infinite phase range and 40 ps worst-case phase resolution at 400 MHz. The architecture uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correctors. This more easily process-portable DLL achieves jitter performance comparable to a more complex analog DLL, when placed into identical high-Speed Interface circuits fabricated on the same die in a 0.4 /spl mu/m CMOS process.
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A 2.6 GB/s multi-purpose chip-to-chip Interface
1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers ISSCC. First Edition (Cat. No.98CH36156), 1Co-Authors: Benedict Lau, Yiu-fai Chan, A. Moncayo, M. Allen, J. Salmon, J. Liu, M. Muthal, Cliff C. Lee, T. NguyenAbstract:A high-Speed Interface cell delivers 800 Mb/s/pin data transfer rate on a 26b wide I/O Interface consisting of a dual-byte data field and a byte-wide command field. For 2.6 GB/s data rate, a 400 MHz clock recovery circuit guarantees the timing margin for transferring 800 mV swing data at both clock edges over the I/O Interface. Data from the high Speed Interface is internally deserialized to provide a 100 MHz (f/4) ASIC clock Interface. A test chip contains three megacells and built-in clock synchronization circuits to ensure proper data transfer between the three megacells with minimal impact on latency. Controlled impedance buses, referred to as channels, with careful PCB layout ensure 800 Mb/s/pin data rate on-board for ASIC-to-ASIC or ASIC-to-DRAM system configuration.
Bruno W Garlepp - One of the best experts on this subject based on the ideXlab platform.
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a portable digital dll for high Speed cmos Interface circuits
IEEE Journal of Solid-state Circuits, 1999Co-Authors: Bruno W Garlepp, Kevin S Donnelly, Jun Kim, Jared L Zerbe, C Huang, Chanh Tran, Clemenz Portmann, D Stark, Park Chau, Yiu-fai ChanAbstract:A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-Speed Interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.
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a portable digital dll architecture for cmos Interface circuits
Symposium on VLSI Circuits, 1998Co-Authors: Bruno W Garlepp, Kevin S Donnelly, Jun Kim, Pak Shing Chau, Jared L Zerbe, C Huang, Chanh Tran, Clemenz Portmann, D Stark, Yiu-fai ChanAbstract:A digital DLL was developed which achieves infinite phase range and 40 ps worst-case phase resolution at 400 MHz. The architecture uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correctors. This more easily process-portable DLL achieves jitter performance comparable to a more complex analog DLL, when placed into identical high-Speed Interface circuits fabricated on the same die in a 0.4 /spl mu/m CMOS process.
D Stark - One of the best experts on this subject based on the ideXlab platform.
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a portable digital dll for high Speed cmos Interface circuits
IEEE Journal of Solid-state Circuits, 1999Co-Authors: Bruno W Garlepp, Kevin S Donnelly, Jun Kim, Jared L Zerbe, C Huang, Chanh Tran, Clemenz Portmann, D Stark, Park Chau, Yiu-fai ChanAbstract:A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-Speed Interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.
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a portable digital dll architecture for cmos Interface circuits
Symposium on VLSI Circuits, 1998Co-Authors: Bruno W Garlepp, Kevin S Donnelly, Jun Kim, Pak Shing Chau, Jared L Zerbe, C Huang, Chanh Tran, Clemenz Portmann, D Stark, Yiu-fai ChanAbstract:A digital DLL was developed which achieves infinite phase range and 40 ps worst-case phase resolution at 400 MHz. The architecture uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correctors. This more easily process-portable DLL achieves jitter performance comparable to a more complex analog DLL, when placed into identical high-Speed Interface circuits fabricated on the same die in a 0.4 /spl mu/m CMOS process.
Clemenz Portmann - One of the best experts on this subject based on the ideXlab platform.
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a portable digital dll for high Speed cmos Interface circuits
IEEE Journal of Solid-state Circuits, 1999Co-Authors: Bruno W Garlepp, Kevin S Donnelly, Jun Kim, Jared L Zerbe, C Huang, Chanh Tran, Clemenz Portmann, D Stark, Park Chau, Yiu-fai ChanAbstract:A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-Speed Interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.
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a portable digital dll architecture for cmos Interface circuits
Symposium on VLSI Circuits, 1998Co-Authors: Bruno W Garlepp, Kevin S Donnelly, Jun Kim, Pak Shing Chau, Jared L Zerbe, C Huang, Chanh Tran, Clemenz Portmann, D Stark, Yiu-fai ChanAbstract:A digital DLL was developed which achieves infinite phase range and 40 ps worst-case phase resolution at 400 MHz. The architecture uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correctors. This more easily process-portable DLL achieves jitter performance comparable to a more complex analog DLL, when placed into identical high-Speed Interface circuits fabricated on the same die in a 0.4 /spl mu/m CMOS process.
Chanh Tran - One of the best experts on this subject based on the ideXlab platform.
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a portable digital dll for high Speed cmos Interface circuits
IEEE Journal of Solid-state Circuits, 1999Co-Authors: Bruno W Garlepp, Kevin S Donnelly, Jun Kim, Jared L Zerbe, C Huang, Chanh Tran, Clemenz Portmann, D Stark, Park Chau, Yiu-fai ChanAbstract:A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-Speed Interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.
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a portable digital dll architecture for cmos Interface circuits
Symposium on VLSI Circuits, 1998Co-Authors: Bruno W Garlepp, Kevin S Donnelly, Jun Kim, Pak Shing Chau, Jared L Zerbe, C Huang, Chanh Tran, Clemenz Portmann, D Stark, Yiu-fai ChanAbstract:A digital DLL was developed which achieves infinite phase range and 40 ps worst-case phase resolution at 400 MHz. The architecture uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correctors. This more easily process-portable DLL achieves jitter performance comparable to a more complex analog DLL, when placed into identical high-Speed Interface circuits fabricated on the same die in a 0.4 /spl mu/m CMOS process.