The Experts below are selected from a list of 147 Experts worldwide ranked by ideXlab platform
Satoshi Sugahara - One of the best experts on this subject based on the ideXlab platform.
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nonvolatile flip flop using pseudo Spin Transistor architecture and its power gating applications
International Semiconductor Conference, 2012Co-Authors: Shuuichirou Yamamoto, Yusuke Shuto, Satoshi SugaharaAbstract:We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-Spin-Transistor architecture using Spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved by its cell structure employing pseudo-Spin-MOSFETs (PS-MOSFETs) that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized lowest BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and systems-on-chip (SoCs) using nonvolatile hierarchical-memory systems that are configured with NV-DFFs and nonvolatile static random access memories (NV-SRAMs).
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nonvolatile power gating field programmable gate array using nonvolatile static random access memory and nonvolatile flip flops based on pseudo Spin Transistor architecture with Spin transfer torque magnetic tunnel junctions
Japanese Journal of Applied Physics, 2012Co-Authors: Shuuichirou Yamamoto, Yusuke Shuto, Satoshi SugaharaAbstract:We proposed and computationally analyzed a nonvolatile power-gating field-programmable gate array (NVPG-FPGA) based on pseudo-Spin-Transistor architecture with Spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits of the NVPG-FPGA. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power gating (PG). The break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET, which allows highly efficient PG operations with fine granularity, were proposed.
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static noise margin and power gating efficiency of a new nonvolatile sram cell based on pseudo Spin Transistor architecture
International Memory Workshop, 2012Co-Authors: Yusuke Shuto, Shuuichirou Yamamoto, Satoshi SugaharaAbstract:Static noise margin (SNM) and power-gating efficiency were computationally analyzed for our proposed nonvolatile SRAM (NV-SRAM) cell based on pseudo-Spin-MOSFET (PS-MOSFET) architecture using Spin-transfer-torque MTJs (STT-MTJs). The NV-SRAM cell has the same SNM as an optimized 6T-SRAM cell. SNM was also evaluated for other recently-proposed NV-SRAM cells using STT-MTJs, and we showed that their SNMs were deteriorated owing to the effect of the constituent STT-MTJs. Break-even time (BET) and power efficiency were analyzed for the NV-SRAM cell using PS-MOSFETs. The BET can be successfully minimized by controlling the bias of the cell. The average power dissipation can be effectively reduced by power-gating (PG) executions, and the further reduction is made possible by introducing a sleep mode (which is a data retention mode using a low power supply voltage).
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evaluation and control of break even time of nonvolatile static random access memory based on Spin Transistor architecture with Spin transfer torque magnetic tunnel junctions
Japanese Journal of Applied Physics, 2012Co-Authors: Satoshi SugaharaAbstract:The energy performance of a nonvolatile static random access memory (NV-SRAM) cell for power gating applications was quantitatively analyzed for the first time using the performance index of break-even time (BET). The NV-SRAM cell is based on Spin-Transistor architecture using ordinary metal–oxide–semiconductor field-effect Transistors (MOSFETs) and Spin-transfer-torque magnetic tunnel junctions (STT-MTJs), whose circuit representation of Spin-Transistor is referred to as a pseudo-Spin-MOSFET (PS-MOSFET). The cell is configured with a standard six-Transistor SRAM cell and two PS-MOSFETs. The NV-SRAM cell basically has a short BET of submicroseconds. Although the write (store) operation to the STT-MTJs causes an increase in the BET, it can be successfully reduced by the proposed power-aware bias-control for the PS-MOSFETs.
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nonvolatile delay flip flop using Spin Transistor architecture with Spin transfer torque mtjs for power gating systems
Electronics Letters, 2011Co-Authors: Shuuichirou Yamamoto, Yusuke Shuto, Satoshi SugaharaAbstract:The power-gating (PG) ability of the authors' previously proposed nonvolatile delay flip-flop (NV-DFF) using pseudo-Spin-Transistors with Spin transfer torque magnetic tunnel junctions (STT-MTJs) is computationally analysed. Break-even time (BET) for nonvolatile logic circuits, which is an important index of energy performance for PG systems, is also formulated for the first time. The BET of the proposed NV-DFF can be effectively reduced by the design of the pseudo-Spin-Transistor parts of the cell. The NV-DFF is applicable to coarse- and fine-grained PG architectures owing to its potential BET of sub-microseconds in practical CMOS logic applications.
Jaroslav Fabian - One of the best experts on this subject based on the ideXlab platform.
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proximity effects in bilayer graphene on monolayer wse_ 2 field effect Spin valley locking Spin orbit valve and Spin Transistor
Physical Review Letters, 2017Co-Authors: Martin Gmitra, Jaroslav FabianAbstract:: Proximity orbital and Spin-orbit effects of bilayer graphene on monolayer WSe_{2} are investigated from first principles. We find that the built-in electric field induces an orbital band gap of about 10 meV in bilayer graphene. Remarkably, the proximity Spin-orbit splitting for holes is 2 orders of magnitude-the Spin-orbit splitting of the valence band at K is about 2 meV-more than for electrons. Effectively, holes experience Spin valley locking due to the strong proximity of the lower graphene layer to WSe_{2}. However, applying an external transverse electric field of some 1 V/nm, countering the built-in field of the heterostructure, completely reverses this effect and allows, instead of holes, electrons to be Spin valley locked with 2 meV Spin-orbit splitting. Such a behavior constitutes a highly efficient field-effect Spin-orbit valve, making bilayer graphene on WSe_{2} a potential platform for a field-effect Spin Transistor.
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proximity effects in bilayer graphene on monolayer wse_ 2 field effect Spin valley locking Spin orbit valve and Spin Transistor
Physical Review Letters, 2017Co-Authors: Martin Gmitra, Jaroslav FabianAbstract:Proximity orbital and Spin-orbit effects of bilayer graphene on monolayer ${\mathrm{WSe}}_{2}$ are investigated from first principles. We find that the built-in electric field induces an orbital band gap of about 10 meV in bilayer graphene. Remarkably, the proximity Spin-orbit splitting for holes is 2 orders of magnitude---the Spin-orbit splitting of the valence band at $K$ is about 2 meV---more than for electrons. Effectively, holes experience Spin valley locking due to the strong proximity of the lower graphene layer to ${\mathrm{WSe}}_{2}$. However, applying an external transverse electric field of some $1\text{ }\text{ }\mathrm{V}/\mathrm{nm}$, countering the built-in field of the heterostructure, completely reverses this effect and allows, instead of holes, electrons to be Spin valley locked with 2 meV Spin-orbit splitting. Such a behavior constitutes a highly efficient field-effect Spin-orbit valve, making bilayer graphene on ${\mathrm{WSe}}_{2}$ a potential platform for a field-effect Spin Transistor.
Yusuke Shuto - One of the best experts on this subject based on the ideXlab platform.
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nonvolatile flip flop using pseudo Spin Transistor architecture and its power gating applications
International Semiconductor Conference, 2012Co-Authors: Shuuichirou Yamamoto, Yusuke Shuto, Satoshi SugaharaAbstract:We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-Spin-Transistor architecture using Spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved by its cell structure employing pseudo-Spin-MOSFETs (PS-MOSFETs) that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized lowest BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and systems-on-chip (SoCs) using nonvolatile hierarchical-memory systems that are configured with NV-DFFs and nonvolatile static random access memories (NV-SRAMs).
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nonvolatile power gating field programmable gate array using nonvolatile static random access memory and nonvolatile flip flops based on pseudo Spin Transistor architecture with Spin transfer torque magnetic tunnel junctions
Japanese Journal of Applied Physics, 2012Co-Authors: Shuuichirou Yamamoto, Yusuke Shuto, Satoshi SugaharaAbstract:We proposed and computationally analyzed a nonvolatile power-gating field-programmable gate array (NVPG-FPGA) based on pseudo-Spin-Transistor architecture with Spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits of the NVPG-FPGA. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power gating (PG). The break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET, which allows highly efficient PG operations with fine granularity, were proposed.
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static noise margin and power gating efficiency of a new nonvolatile sram cell based on pseudo Spin Transistor architecture
International Memory Workshop, 2012Co-Authors: Yusuke Shuto, Shuuichirou Yamamoto, Satoshi SugaharaAbstract:Static noise margin (SNM) and power-gating efficiency were computationally analyzed for our proposed nonvolatile SRAM (NV-SRAM) cell based on pseudo-Spin-MOSFET (PS-MOSFET) architecture using Spin-transfer-torque MTJs (STT-MTJs). The NV-SRAM cell has the same SNM as an optimized 6T-SRAM cell. SNM was also evaluated for other recently-proposed NV-SRAM cells using STT-MTJs, and we showed that their SNMs were deteriorated owing to the effect of the constituent STT-MTJs. Break-even time (BET) and power efficiency were analyzed for the NV-SRAM cell using PS-MOSFETs. The BET can be successfully minimized by controlling the bias of the cell. The average power dissipation can be effectively reduced by power-gating (PG) executions, and the further reduction is made possible by introducing a sleep mode (which is a data retention mode using a low power supply voltage).
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nonvolatile delay flip flop using Spin Transistor architecture with Spin transfer torque mtjs for power gating systems
Electronics Letters, 2011Co-Authors: Shuuichirou Yamamoto, Yusuke Shuto, Satoshi SugaharaAbstract:The power-gating (PG) ability of the authors' previously proposed nonvolatile delay flip-flop (NV-DFF) using pseudo-Spin-Transistors with Spin transfer torque magnetic tunnel junctions (STT-MTJs) is computationally analysed. Break-even time (BET) for nonvolatile logic circuits, which is an important index of energy performance for PG systems, is also formulated for the first time. The BET of the proposed NV-DFF can be effectively reduced by the design of the pseudo-Spin-Transistor parts of the cell. The NV-DFF is applicable to coarse- and fine-grained PG architectures owing to its potential BET of sub-microseconds in practical CMOS logic applications.
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a new Spin functional metal oxide semiconductor field effect Transistor based on magnetic tunnel junction technology pseudo Spin mosfet
Applied Physics Express, 2010Co-Authors: Yusuke Shuto, Masaaki Tanaka, Shuuichirou Yamamoto, Ryosho Nakane, Wenhong Wang, Hiroaki Sukegawa, Koichiro Inomata, Satoshi SugaharaAbstract:We fabricated and characterized a new Spin-functional metal–oxide–semiconductor field-effect Transistor (MOSFET) referred to as a pseudo-Spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit using an ordinary MOSFET and magnetic tunnel junction (MTJ) for reproducing functions of Spin-Transistors. Device integration techniques for a bottom gate MOSFET using a silicon-on-insulator (SOI) substrate and for an MTJ with a full-Heusler alloy electrode and MgO tunnel barrier were developed. The fabricated PS-MOSFET exhibited high and low transconductance controlled by the magnetization configurations of the MTJ at room temperature. This is the first observation of Spin-Transistor operations for Spin-functional MOSFETs.
Martin Gmitra - One of the best experts on this subject based on the ideXlab platform.
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proximity effects in bilayer graphene on monolayer wse_ 2 field effect Spin valley locking Spin orbit valve and Spin Transistor
Physical Review Letters, 2017Co-Authors: Martin Gmitra, Jaroslav FabianAbstract:: Proximity orbital and Spin-orbit effects of bilayer graphene on monolayer WSe_{2} are investigated from first principles. We find that the built-in electric field induces an orbital band gap of about 10 meV in bilayer graphene. Remarkably, the proximity Spin-orbit splitting for holes is 2 orders of magnitude-the Spin-orbit splitting of the valence band at K is about 2 meV-more than for electrons. Effectively, holes experience Spin valley locking due to the strong proximity of the lower graphene layer to WSe_{2}. However, applying an external transverse electric field of some 1 V/nm, countering the built-in field of the heterostructure, completely reverses this effect and allows, instead of holes, electrons to be Spin valley locked with 2 meV Spin-orbit splitting. Such a behavior constitutes a highly efficient field-effect Spin-orbit valve, making bilayer graphene on WSe_{2} a potential platform for a field-effect Spin Transistor.
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proximity effects in bilayer graphene on monolayer wse_ 2 field effect Spin valley locking Spin orbit valve and Spin Transistor
Physical Review Letters, 2017Co-Authors: Martin Gmitra, Jaroslav FabianAbstract:Proximity orbital and Spin-orbit effects of bilayer graphene on monolayer ${\mathrm{WSe}}_{2}$ are investigated from first principles. We find that the built-in electric field induces an orbital band gap of about 10 meV in bilayer graphene. Remarkably, the proximity Spin-orbit splitting for holes is 2 orders of magnitude---the Spin-orbit splitting of the valence band at $K$ is about 2 meV---more than for electrons. Effectively, holes experience Spin valley locking due to the strong proximity of the lower graphene layer to ${\mathrm{WSe}}_{2}$. However, applying an external transverse electric field of some $1\text{ }\text{ }\mathrm{V}/\mathrm{nm}$, countering the built-in field of the heterostructure, completely reverses this effect and allows, instead of holes, electrons to be Spin valley locked with 2 meV Spin-orbit splitting. Such a behavior constitutes a highly efficient field-effect Spin-orbit valve, making bilayer graphene on ${\mathrm{WSe}}_{2}$ a potential platform for a field-effect Spin Transistor.
Shuuichirou Yamamoto - One of the best experts on this subject based on the ideXlab platform.
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nonvolatile flip flop using pseudo Spin Transistor architecture and its power gating applications
International Semiconductor Conference, 2012Co-Authors: Shuuichirou Yamamoto, Yusuke Shuto, Satoshi SugaharaAbstract:We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-Spin-Transistor architecture using Spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved by its cell structure employing pseudo-Spin-MOSFETs (PS-MOSFETs) that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized lowest BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and systems-on-chip (SoCs) using nonvolatile hierarchical-memory systems that are configured with NV-DFFs and nonvolatile static random access memories (NV-SRAMs).
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nonvolatile power gating field programmable gate array using nonvolatile static random access memory and nonvolatile flip flops based on pseudo Spin Transistor architecture with Spin transfer torque magnetic tunnel junctions
Japanese Journal of Applied Physics, 2012Co-Authors: Shuuichirou Yamamoto, Yusuke Shuto, Satoshi SugaharaAbstract:We proposed and computationally analyzed a nonvolatile power-gating field-programmable gate array (NVPG-FPGA) based on pseudo-Spin-Transistor architecture with Spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits of the NVPG-FPGA. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power gating (PG). The break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET, which allows highly efficient PG operations with fine granularity, were proposed.
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static noise margin and power gating efficiency of a new nonvolatile sram cell based on pseudo Spin Transistor architecture
International Memory Workshop, 2012Co-Authors: Yusuke Shuto, Shuuichirou Yamamoto, Satoshi SugaharaAbstract:Static noise margin (SNM) and power-gating efficiency were computationally analyzed for our proposed nonvolatile SRAM (NV-SRAM) cell based on pseudo-Spin-MOSFET (PS-MOSFET) architecture using Spin-transfer-torque MTJs (STT-MTJs). The NV-SRAM cell has the same SNM as an optimized 6T-SRAM cell. SNM was also evaluated for other recently-proposed NV-SRAM cells using STT-MTJs, and we showed that their SNMs were deteriorated owing to the effect of the constituent STT-MTJs. Break-even time (BET) and power efficiency were analyzed for the NV-SRAM cell using PS-MOSFETs. The BET can be successfully minimized by controlling the bias of the cell. The average power dissipation can be effectively reduced by power-gating (PG) executions, and the further reduction is made possible by introducing a sleep mode (which is a data retention mode using a low power supply voltage).
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nonvolatile delay flip flop using Spin Transistor architecture with Spin transfer torque mtjs for power gating systems
Electronics Letters, 2011Co-Authors: Shuuichirou Yamamoto, Yusuke Shuto, Satoshi SugaharaAbstract:The power-gating (PG) ability of the authors' previously proposed nonvolatile delay flip-flop (NV-DFF) using pseudo-Spin-Transistors with Spin transfer torque magnetic tunnel junctions (STT-MTJs) is computationally analysed. Break-even time (BET) for nonvolatile logic circuits, which is an important index of energy performance for PG systems, is also formulated for the first time. The BET of the proposed NV-DFF can be effectively reduced by the design of the pseudo-Spin-Transistor parts of the cell. The NV-DFF is applicable to coarse- and fine-grained PG architectures owing to its potential BET of sub-microseconds in practical CMOS logic applications.
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nonvolatile delay flip flop based on Spin Transistor architecture and its power gating applications
Japanese Journal of Applied Physics, 2010Co-Authors: Shuuichirou Yamamoto, Satoshi SugaharaAbstract:We propose and computationally analyze a new type of nonvolatile delay flip-flop (NV-DFF) based on Spin-Transistor architecture, in which pseudo-SpinTransistors consisting of an ordinary metal–oxide–semiconductor filed-effect Transistor (MOSFET) and a magnetic tunnel junction, referred to as pseudo-Spin-MOSFETs are used as a functional nonvolatile storage element. The proposed circuit not only operates as an ordinary DFF, but also is shut down without losing its data. The NV-DFF has only slight increases in circuit delay and layout area within 10% in comparison with an ordinary DFF. Analysis of break-even time (one of the indices for evaluating power-gating efficiency) reveals that the proposed NV-DFF is acceptable for power-gating architecture.