The Experts below are selected from a list of 120 Experts worldwide ranked by ideXlab platform
Massimo Alioto - One of the best experts on this subject based on the ideXlab platform.
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reconfigurable sleep transistor for gidl reduction in ultra low Standby Power Systems
Custom Integrated Circuits Conference, 2012Co-Authors: Suyoung Bang, David Blaauw, Dennis Sylvester, Massimo AliotoAbstract:Standby Power reduction is critical to battery life and volume reduction in mm-scale sensor nodes. Power gating is extensively adopted to reduce leakage, but the inserted sleep transistors can suffer from other leakage mechanisms, namely GIDL, which become dominant at battery voltages of 3 V or higher. This paper introduces the concept of reconfigurable sleep transistors, in which two different topologies are used in active versus sleep mode. In active mode, transistors are stacked as in traditional Power gating schemes. In sleep mode, sleep transistors are reconfigured to reduce GIDL current, in addition to subthreshold leakage. Measurements on a 180nm CMOS test chip shows 12.6× Standby leakage reduction at V DD =4.0 V and T=25°C. This improvement comes with acceptable area penalty due to additional small reconfiguration transistors and separate body contacts, and no impact on active mode operation.
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CICC - Reconfigurable sleep transistor for GIDL reduction in ultra-low Standby Power Systems
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012Co-Authors: Suyoung Bang, David Blaauw, Dennis Sylvester, Massimo AliotoAbstract:Standby Power reduction is critical to battery life and volume reduction in mm-scale sensor nodes. Power gating is extensively adopted to reduce leakage, but the inserted sleep transistors can suffer from other leakage mechanisms, namely GIDL, which become dominant at battery voltages of 3 V or higher. This paper introduces the concept of reconfigurable sleep transistors, in which two different topologies are used in active versus sleep mode. In active mode, transistors are stacked as in traditional Power gating schemes. In sleep mode, sleep transistors are reconfigured to reduce GIDL current, in addition to subthreshold leakage. Measurements on a 180nm CMOS test chip shows 12.6× Standby leakage reduction at V DD =4.0 V and T=25°C. This improvement comes with acceptable area penalty due to additional small reconfiguration transistors and separate body contacts, and no impact on active mode operation.
Douglas C. Folts - One of the best experts on this subject based on the ideXlab platform.
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UPS response to Power disturbances-a proposed method for determination of UPS response to Power disturbances
Proceedings of 1994 IEEE Applied Power Electronics Conference and Exposition - ASPEC'94, 1Co-Authors: D.s. Dorr, Douglas C. FoltsAbstract:The time it takes for a backup Power system (BPS) to transfer to battery Power (i.e. "transfer time") is difficult to measure. No industry standard exists describing a reasonable test for this measurement. A technique for inducing Power interruptions and then measuring BPS output voltage response is described. Power interruptions at reduced voltage are recommended because data analysis from a North American Power Quality Study by National Power Laboratory show that 81 percent of all interruptions occur during a low voltage condition. Examples of the proposed measurement technique are shown for a variety of BPS topologies. Experimental results illustrate the difference between uninterruptible and Standby Power Systems. >
Suyoung Bang - One of the best experts on this subject based on the ideXlab platform.
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reconfigurable sleep transistor for gidl reduction in ultra low Standby Power Systems
Custom Integrated Circuits Conference, 2012Co-Authors: Suyoung Bang, David Blaauw, Dennis Sylvester, Massimo AliotoAbstract:Standby Power reduction is critical to battery life and volume reduction in mm-scale sensor nodes. Power gating is extensively adopted to reduce leakage, but the inserted sleep transistors can suffer from other leakage mechanisms, namely GIDL, which become dominant at battery voltages of 3 V or higher. This paper introduces the concept of reconfigurable sleep transistors, in which two different topologies are used in active versus sleep mode. In active mode, transistors are stacked as in traditional Power gating schemes. In sleep mode, sleep transistors are reconfigured to reduce GIDL current, in addition to subthreshold leakage. Measurements on a 180nm CMOS test chip shows 12.6× Standby leakage reduction at V DD =4.0 V and T=25°C. This improvement comes with acceptable area penalty due to additional small reconfiguration transistors and separate body contacts, and no impact on active mode operation.
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CICC - Reconfigurable sleep transistor for GIDL reduction in ultra-low Standby Power Systems
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012Co-Authors: Suyoung Bang, David Blaauw, Dennis Sylvester, Massimo AliotoAbstract:Standby Power reduction is critical to battery life and volume reduction in mm-scale sensor nodes. Power gating is extensively adopted to reduce leakage, but the inserted sleep transistors can suffer from other leakage mechanisms, namely GIDL, which become dominant at battery voltages of 3 V or higher. This paper introduces the concept of reconfigurable sleep transistors, in which two different topologies are used in active versus sleep mode. In active mode, transistors are stacked as in traditional Power gating schemes. In sleep mode, sleep transistors are reconfigured to reduce GIDL current, in addition to subthreshold leakage. Measurements on a 180nm CMOS test chip shows 12.6× Standby leakage reduction at V DD =4.0 V and T=25°C. This improvement comes with acceptable area penalty due to additional small reconfiguration transistors and separate body contacts, and no impact on active mode operation.
D.s. Dorr - One of the best experts on this subject based on the ideXlab platform.
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UPS response to Power disturbances-a proposed method for determination of UPS response to Power disturbances
Proceedings of 1994 IEEE Applied Power Electronics Conference and Exposition - ASPEC'94, 1Co-Authors: D.s. Dorr, Douglas C. FoltsAbstract:The time it takes for a backup Power system (BPS) to transfer to battery Power (i.e. "transfer time") is difficult to measure. No industry standard exists describing a reasonable test for this measurement. A technique for inducing Power interruptions and then measuring BPS output voltage response is described. Power interruptions at reduced voltage are recommended because data analysis from a North American Power Quality Study by National Power Laboratory show that 81 percent of all interruptions occur during a low voltage condition. Examples of the proposed measurement technique are shown for a variety of BPS topologies. Experimental results illustrate the difference between uninterruptible and Standby Power Systems. >
David Blaauw - One of the best experts on this subject based on the ideXlab platform.
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reconfigurable sleep transistor for gidl reduction in ultra low Standby Power Systems
Custom Integrated Circuits Conference, 2012Co-Authors: Suyoung Bang, David Blaauw, Dennis Sylvester, Massimo AliotoAbstract:Standby Power reduction is critical to battery life and volume reduction in mm-scale sensor nodes. Power gating is extensively adopted to reduce leakage, but the inserted sleep transistors can suffer from other leakage mechanisms, namely GIDL, which become dominant at battery voltages of 3 V or higher. This paper introduces the concept of reconfigurable sleep transistors, in which two different topologies are used in active versus sleep mode. In active mode, transistors are stacked as in traditional Power gating schemes. In sleep mode, sleep transistors are reconfigured to reduce GIDL current, in addition to subthreshold leakage. Measurements on a 180nm CMOS test chip shows 12.6× Standby leakage reduction at V DD =4.0 V and T=25°C. This improvement comes with acceptable area penalty due to additional small reconfiguration transistors and separate body contacts, and no impact on active mode operation.
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CICC - Reconfigurable sleep transistor for GIDL reduction in ultra-low Standby Power Systems
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012Co-Authors: Suyoung Bang, David Blaauw, Dennis Sylvester, Massimo AliotoAbstract:Standby Power reduction is critical to battery life and volume reduction in mm-scale sensor nodes. Power gating is extensively adopted to reduce leakage, but the inserted sleep transistors can suffer from other leakage mechanisms, namely GIDL, which become dominant at battery voltages of 3 V or higher. This paper introduces the concept of reconfigurable sleep transistors, in which two different topologies are used in active versus sleep mode. In active mode, transistors are stacked as in traditional Power gating schemes. In sleep mode, sleep transistors are reconfigured to reduce GIDL current, in addition to subthreshold leakage. Measurements on a 180nm CMOS test chip shows 12.6× Standby leakage reduction at V DD =4.0 V and T=25°C. This improvement comes with acceptable area penalty due to additional small reconfiguration transistors and separate body contacts, and no impact on active mode operation.