The Experts below are selected from a list of 5115 Experts worldwide ranked by ideXlab platform
D.c. Wunsch - One of the best experts on this subject based on the ideXlab platform.
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a comparison of the decision tree approach and the neural networks based heuristic dynamic programming approach for Subcircuit extraction problem
Intelligent computing : theory and applications. Conference, 2003Co-Authors: Nian Zhang, D.c. WunschAbstract:The applications of non-standard logic device are increasing fast in the industry. Many of these applications require high speed, low power, functionality and flexibility, which cannot be obtained by standard logic device. These special logic cells can be constructed by the topology design strategy automatically or manually. However, the need arises for the topology design verification. The layout versus schematic (LVS) analysis is an essential part of topology design verification, and Subcircuit extraction is one of the operations in the LVS testing. In this paper, we first provided an efficient decision tree approach to the graph isomorphism problem, and then effectively applied it to the Subcircuit extraction problem based on the solution to the graph isomorphism problem. To evaluate its performance, we compare it with the neural networks based heuristic dynamic programming algorithm (SubHDP) which is by far one of the fastest algorithms for Subcircuit extraction problem.
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A fuzzy attributed graph approach to Subcircuit extraction problem
The 12th IEEE International Conference on Fuzzy Systems 2003. FUZZ '03., 2003Co-Authors: Nian Zhang, D.c. WunschAbstract:Fuzzy attributed graph (FAG) is not only widely used in the fields of image understanding and pattern recognition, but is useful to fuzzy graph matching problem. One of the applications of fuzzy graph matching is the Subcircuit extraction problem. Subcircuit extraction problem is very important for VLSI testing, layout versus schematic (LVS) check, and circuit partition, etc. In this paper, fuzzy attributed graph (FAG) is first effectively applied to the subgraph isomorphism problem. And then we provide an efficient fuzzy attributed graph algorithm based on the solution to subgraph isomorphism for the Subcircuit extraction problem. Similarity measurement makes a significant contribution to both the subgraph isomorphism problem and the Subcircuit extraction problem.
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FUZZ-IEEE - A fuzzy attributed graph approach to Subcircuit extraction problem
The 12th IEEE International Conference on Fuzzy Systems 2003. FUZZ '03., 2003Co-Authors: Nian Zhang, D.c. WunschAbstract:Fuzzy attributed graph (FAG) is not only widely used in the fields of image understanding and pattern recognition, but is useful to fuzzy graph matching problem. One of the applications of fuzzy graph matching is the Subcircuit extraction problem. Subcircuit extraction problem is very important for VLSI testing, layout versus schematic (LVS) check, and circuit partition, etc. In this paper, fuzzy attributed graph (FAG) is first effectively applied to the subgraph isomorphism problem. And then we provide an efficient fuzzy attributed graph algorithm based on the solution to subgraph isomorphism for the Subcircuit extraction problem. Similarity measurement makes a significant contribution to both the subgraph isomorphism problem and the Subcircuit extraction problem.
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The Subcircuit extraction problem
IEEE Potentials, 2003Co-Authors: Nian Zhang, D.c. Wunsch, F. HararyAbstract:The steady down scaling of CMOS device dimensions has been the main stimulus to the growth of microelectronics and computer aided very large scale integration (VLSI) design. But the more an integrated circuit (IC) is scaled, the higher its packing density becomes. The increasing size of chips, measured in either area or number of transistors, and the waste of the large capital investment involved in fabricating and testing circuits that do not work, make layout analysis and verification an important part of physical design automation. The most efficient way to overcome these difficulties is to identify a related collection of interconnected primitive devices in a circuit as a gate-level component. This is usually called the Subcircuit extraction problem. The paper presents some background on Subcircuit extraction. Subcircuit extraction is becoming a more critical issue with the increasing design sizes of very large scale integrated circuits (VLSICs). In the future, one of the most important tasks is to convert current stand-alone Subcircuit extraction algorithms into economic benefits. We should make every effort to find those companies who would like to incorporate these algorithms into their VLSI layout verification software to speed up the process.
Nian Zhang - One of the best experts on this subject based on the ideXlab platform.
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a comparison of the decision tree approach and the neural networks based heuristic dynamic programming approach for Subcircuit extraction problem
Intelligent computing : theory and applications. Conference, 2003Co-Authors: Nian Zhang, D.c. WunschAbstract:The applications of non-standard logic device are increasing fast in the industry. Many of these applications require high speed, low power, functionality and flexibility, which cannot be obtained by standard logic device. These special logic cells can be constructed by the topology design strategy automatically or manually. However, the need arises for the topology design verification. The layout versus schematic (LVS) analysis is an essential part of topology design verification, and Subcircuit extraction is one of the operations in the LVS testing. In this paper, we first provided an efficient decision tree approach to the graph isomorphism problem, and then effectively applied it to the Subcircuit extraction problem based on the solution to the graph isomorphism problem. To evaluate its performance, we compare it with the neural networks based heuristic dynamic programming algorithm (SubHDP) which is by far one of the fastest algorithms for Subcircuit extraction problem.
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A fuzzy attributed graph approach to Subcircuit extraction problem
The 12th IEEE International Conference on Fuzzy Systems 2003. FUZZ '03., 2003Co-Authors: Nian Zhang, D.c. WunschAbstract:Fuzzy attributed graph (FAG) is not only widely used in the fields of image understanding and pattern recognition, but is useful to fuzzy graph matching problem. One of the applications of fuzzy graph matching is the Subcircuit extraction problem. Subcircuit extraction problem is very important for VLSI testing, layout versus schematic (LVS) check, and circuit partition, etc. In this paper, fuzzy attributed graph (FAG) is first effectively applied to the subgraph isomorphism problem. And then we provide an efficient fuzzy attributed graph algorithm based on the solution to subgraph isomorphism for the Subcircuit extraction problem. Similarity measurement makes a significant contribution to both the subgraph isomorphism problem and the Subcircuit extraction problem.
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FUZZ-IEEE - A fuzzy attributed graph approach to Subcircuit extraction problem
The 12th IEEE International Conference on Fuzzy Systems 2003. FUZZ '03., 2003Co-Authors: Nian Zhang, D.c. WunschAbstract:Fuzzy attributed graph (FAG) is not only widely used in the fields of image understanding and pattern recognition, but is useful to fuzzy graph matching problem. One of the applications of fuzzy graph matching is the Subcircuit extraction problem. Subcircuit extraction problem is very important for VLSI testing, layout versus schematic (LVS) check, and circuit partition, etc. In this paper, fuzzy attributed graph (FAG) is first effectively applied to the subgraph isomorphism problem. And then we provide an efficient fuzzy attributed graph algorithm based on the solution to subgraph isomorphism for the Subcircuit extraction problem. Similarity measurement makes a significant contribution to both the subgraph isomorphism problem and the Subcircuit extraction problem.
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The Subcircuit extraction problem
IEEE Potentials, 2003Co-Authors: Nian Zhang, D.c. Wunsch, F. HararyAbstract:The steady down scaling of CMOS device dimensions has been the main stimulus to the growth of microelectronics and computer aided very large scale integration (VLSI) design. But the more an integrated circuit (IC) is scaled, the higher its packing density becomes. The increasing size of chips, measured in either area or number of transistors, and the waste of the large capital investment involved in fabricating and testing circuits that do not work, make layout analysis and verification an important part of physical design automation. The most efficient way to overcome these difficulties is to identify a related collection of interconnected primitive devices in a circuit as a gate-level component. This is usually called the Subcircuit extraction problem. The paper presents some background on Subcircuit extraction. Subcircuit extraction is becoming a more critical issue with the increasing design sizes of very large scale integrated circuits (VLSICs). In the future, one of the most important tasks is to convert current stand-alone Subcircuit extraction algorithms into economic benefits. We should make every effort to find those companies who would like to incorporate these algorithms into their VLSI layout verification software to speed up the process.
Zuhui Chen - One of the best experts on this subject based on the ideXlab platform.
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Subcircuit compact model for dopant segregated
2010Co-Authors: Schottky Gateallaround, Xing Zhou, Yokeking Chin, Junbin Zhang, Zuhui ChenAbstract:In this paper, we demonstrate analytical device mod- els and a unique Subcircuit approach to physically and accurately model the dopant-segregated Schottky (DSS) gate-all-around (GAA) Si-nanowire (SiNW) MOSFETs. The direct current char- acteristics of the DSS GAA SiNW MOSFETs are investigated through numerical simulations and fabricated devices. Transport mechanisms are studied and explained with numerical devices from ambipolar thermionic tunneling to unipolar drift-diffusion and a combination of both as the dopant segregation doping and thickness are varied. The convex curvature in the Ids-Vds characteristics is accurately reproduced by the Subcircuit compact model, and it is shown for the first time that such a unique gds-Vds characteristic in DSS devices is only feasible to be modeled by the Subcircuit approach. Index Terms—Ambipolar, compact model, dopant-segregated Schottky (DSS), drift-diffusion (DD), gate-all-around (GAA), gate-induced drain leakage (GIDL), MOSFET, Schottky barrier (SB), Subcircuit, thermionic tunneling (TT), unipolar.
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Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs
IEEE Transactions on Electron Devices, 2010Co-Authors: Xing Zhou, Yokeking Chin, Junbin Zhang, Zuhui ChenAbstract:In this paper, we demonstrate analytical device models and a unique Subcircuit approach to physically and accurately model the dopant-segregated Schottky (DSS) gate-all-around (GAA) Si-nanowire (SiNW) MOSFETs. The direct current characteristics of the DSS GAA SiNW MOSFETs are investigated through numerical simulations and fabricated devices. Transport mechanisms are studied and explained with numerical devices from ambipolar thermionic tunneling to unipolar drift-diffusion and a combination of both as the dopant segregation doping and thickness are varied. The convex curvature in the Ids- Vds characteristics is accurately reproduced by the Subcircuit compact model, and it is shown for the first time that such a unique gds-Vds characteristic in DSS devices is only feasible to be modeled by the Subcircuit approach.
Shuenn-der Tzeng - One of the best experts on this subject based on the ideXlab platform.
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A novel Subcircuit extraction algorithm by recursive identification scheme
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001Co-Authors: Wei-hsin Chang, Shuenn-der TzengAbstract:To extract Subcircuits from a large circuit netlist is an important task that contributes a lot in many fields of computer aided design. In this paper, a novel Subcircuit extraction algorithm-DECIDE, based on a recursive graph identification scheme as well as a fast graph construction approach is presented. Cooperating with a proper weighting function that assigns a weighting value to each node, the number of nodes needed to be recognized decreases such that the required run time is reduced significantly. In addition, the proposed algorithm is technology independent and can be applied to handle circuits of any design style.
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ISCAS (5) - A novel Subcircuit extraction algorithm by recursive identification scheme
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001Co-Authors: Wei-hsin Chang, Shuenn-der TzengAbstract:To extract Subcircuits from a large circuit netlist is an important task that contributes a lot in many fields of computer aided design. In this paper, a novel Subcircuit extraction algorithm-DECIDE, based on a recursive graph identification scheme as well as a fast graph construction approach is presented. Cooperating with a proper weighting function that assigns a weighting value to each node, the number of nodes needed to be recognized decreases such that the required run time is reduced significantly. In addition, the proposed algorithm is technology independent and can be applied to handle circuits of any design style.
B. Mason - One of the best experts on this subject based on the ideXlab platform.
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A SPICE compatible Subcircuit model for lateral bipolar transistors in a CMOS process
IEEE Transactions on Electron Devices, 1998Co-Authors: D. Macsweeney, K.g. Mccarthy, A. Mathewson, B. MasonAbstract:This paper describes a SPICE compatible Subcircuit model of a lateral pnp transistor, which was fabricated in a 0.6 /spl mu/m CMOS process. The extraction of a dc parameter set for the lateral device is more complicated than for a vertical device because of the presence of two parasitic vertical bipolar transistors which are formed by the emitter/collector, the base and the substrate regions. The SPICE Gummel-Poon model does not predict the substrate current accurately. This paper proposes a method which involves the use of a Subcircuit incorporating three SPICE Gummel-Poon models [representing one lateral and two parasitic vertical bipolar junction transistors (BJT's)]. The development of this model, its implementation and the results obtained are outlined and discussed. This circuit model is SPICE compatible and can thus be used in commercial simulators. The model provides good agreement over a wide range of measured dc data including substrate current prediction.
