The Experts below are selected from a list of 4470 Experts worldwide ranked by ideXlab platform
Shinichi Takagi - One of the best experts on this subject based on the ideXlab platform.
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high ion ioff and low Subthreshold Slope planar type ingaas tunnel field effect transistors with zn diffused source junctions
Journal of Applied Physics, 2015Co-Authors: M Noguchi, Sanghyeon Kim, Masafumi Yokoyama, Osamu Ichikawa, Takenori Osada, Masahiko Hata, Mitsuru Takenaka, Shinichi TakagiAbstract:We have demonstrated the operation of high on-off current ratio (Ion/Ioff) and low Subthreshold Slope planar-type InGaAs tunnel field effect transistors (TFETs) with Zn-diffused source junctions. The solid-phase Zn diffusion process has been shown to form defect-less p+/n source junctions with steep profiles because of the inherent nature of Zn diffusion into InGaAs, which has significantly improved the TFET performance. The devices presented in this paper have exhibited a record low Subthreshold Slope of 64 mV/dec for planar-type III-V TFETs and a large Ion/Ioff ratio of more than 106 at the same time.
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high i on i off and low Subthreshold Slope planar type ingaas tunnel fets with zn diffused source junctions
International Electron Devices Meeting, 2013Co-Authors: M Noguchi, Sanghyeon Kim, Masafumi Yokoyama, Osamu Ichikawa, Takenori Osada, Masahiko Hata, Mitsuru Takenaka, Shinichi TakagiAbstract:We have demonstrated the operation of high Ion/Ioff and low Subthreshold Slope planar-type InGaAs Tunnel FETs with Zn-diffused source junctions. It has been found that the solid-phase Zn diffusion can form steep-profile and defect-less p+/n source junctions because of the inherent nature of Zn diffusion into InGaAs, which has significantly improved the TFET performance. The present devices have exhibited the record small S.S. of 64 mV/dec and large Ion/Ioff ratio over106 as the planar-type III-V TFETs.
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device design for Subthreshold Slope and threshold voltage control in sub 100 nm fully depleted soi mosfets
IEEE Transactions on Electron Devices, 2004Co-Authors: T Numata, Shinichi TakagiAbstract:This paper presents the comparative study on the device design method of the Subthreshold Slope and the threshold voltage control in fully-depleted silicon-on-insulator MOSFETs under sub-100-nm regime. As for the threshold voltage adjustment method, the combination of the back gate bias and the gate work function controls is found to provide the superior short channel effects, the suppression of the threshold voltage fluctuation due to the SOI thickness variation, and the current drive improvement. As for the Subthreshold Slope, the importance and the necessity of buried oxide engineering are pointed out from the viewpoint of both the substrate capacitance and short-channel effects. It is shown, consequently, that the optimization of the thickness and the permittivity of buried oxides have a significant impact on the control of the Subthreshold Slope under sub-100-nm regime. When the gate length is less than 100 nm, the Subthreshold Slope has a minimum value at the buried oxide thickness of around 40 nm, irrespective of the SOI thickness. It is also shown that the reduction in the permittivity of the buried oxides under a constant buried oxide capacitance improves the Subthreshold Slope.
Takayuki Mori - One of the best experts on this subject based on the ideXlab platform.
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precise transient mechanism of steep Subthreshold Slope pn body tied soi fet and proposal of a new structure for reducing leakage current upon turn off
International Conference on Simulation of Semiconductor Processes and Devices, 2019Co-Authors: Takayuki Mori, Jiro Ida, Hiroki Endo, Y AraiAbstract:In this study, the precise transient mechanism of the super-steep Subthreshold Slope PN-body-tied (PNBT) silicon on insulator field-effect transistor (SOI-FET) is clarified by using technology computer-aided design. We found out that the operation mechanism differs between the turn-on and turn-off. Additionally, a new PNBT SOI-FET structure with a second gate for the high-speed operation is proposed and we showed that the new structure can reduce the leakage current upon the turn-off.
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p channel and n channel super steep Subthreshold Slope pn body tied soi fet for ultralow power cmos
IEEE Journal of the Electron Devices Society, 2018Co-Authors: Takayuki Mori, Jiro IdaAbstract:In this paper, n-channel and p-channel super-steep Subthreshold Slope (SS) PN-body tied (PNBT) silicon on insulator field-effect transistors (SOI-FETs) are demonstrated. The PNBT structure has a symmetrical source and drain structure. The devices show super-steep SS ( $\mu$ m) and high on/off ratio (up to 6 decades) with low drain voltage (Vd = ± 0.1 V), good output characteristics, and threshold voltage controllability. The devices have a body current and a hysteresis characteristic; however, these can be suppressed under proper device conditions. The operation mechanism of the PNBT SOI-FET is clarified by simulation, and an inherent thyristor on the PNBT structure plays a significant role. Both the p-channel and n-channel PNBT SOI-FET characteristics are discussed, and it is indicated that an ultralow power complementary metal-oxide-semiconductor can be realized by the PNBT SOI-FET.
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first experimental confirmation of ultralow voltage rectification by super steep Subthreshold Slope pn body tied soi fet for high efficiency rf energy harvesting and ultralow voltage sensing
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2018Co-Authors: Shun Momose, Takayuki Mori, Jiro Ida, Kenji Itoh, Koichiro Ishibashi, Takuya Yamada, Y AraiAbstract:Rectification of the ultralow voltage signal, up to 10mV, was experimentally confirmed, for the first time, by our new device of the super steep Subthreshold Slope “PN-body Tied SOI-FET” (PNBT-FET). It comes from the surprisingly sharp turn-on characteristics of PNBT-FET, even with measuring on the ultra small voltage range. It is impossible with the conventional diodes, due to becoming the tangential line. Rectification up to 30 MHz was also confirmed with PNBT-FET. It is a good news for PNBT-FET because its conduction mechanism has the low speed concern. Those rectification demonstrations will be promising for small voltage rectification on RF energy harvesting and ultralow voltage sensing applications.
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diode characteristics of a super steep Subthreshold Slope pn body tied soi fet for energy harvesting applications
IEEE Journal of the Electron Devices Society, 2018Co-Authors: Takayuki Mori, Jiro Ida, Shun Momose, Kenji Itoh, Koichiro Ishibashi, Yasuo AraiAbstract:In this paper, the diode characteristics of our newly proposed super-steep Subthreshold Slope “PN-body tied (PNBT) silicon-on-insulator field-effect transistor” are presented, and compared with conventional diodes. We report that the device possesses super-steep characteristics, low leakage current, and sharp turn-on characteristics, even in the ultralow voltage range (50 mV). These indicate that the PNBT diode can potentially be used in high-efficiency rectification for energy harvesting, particularly in situations where there is ultralow input power. In addition, the hysteresis characteristics and the slight shift of the voltage at zero current are confirmed as specific characteristics of PNBT diodes.
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p channel super steep Subthreshold Slope pn body tied soi fet possibility of cmos
IEEE Electron Devices Technology and Manufacturing Conference, 2018Co-Authors: Takayuki Mori, Takahiro Yoshida, Jiro Ida, Yasuo AraiAbstract:We demonstrated a P-channel super steep Subthreshold Slope (SS) PN-Body Tied (PNBT) SOI FET, for the first time. We found out that the substrate bias is necessary for the appearance of the super steep SS on the P-channel PNBT. The device shows a super steep SS (<2mV/dec) keeping a low leakage current (< 1pA}/mum}) with an ultralow drain voltage (0.1V). It has also a very small hysteresis characteristic.
Yasuo Arai - One of the best experts on this subject based on the ideXlab platform.
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diode characteristics of a super steep Subthreshold Slope pn body tied soi fet for energy harvesting applications
IEEE Journal of the Electron Devices Society, 2018Co-Authors: Takayuki Mori, Jiro Ida, Shun Momose, Kenji Itoh, Koichiro Ishibashi, Yasuo AraiAbstract:In this paper, the diode characteristics of our newly proposed super-steep Subthreshold Slope “PN-body tied (PNBT) silicon-on-insulator field-effect transistor” are presented, and compared with conventional diodes. We report that the device possesses super-steep characteristics, low leakage current, and sharp turn-on characteristics, even in the ultralow voltage range (50 mV). These indicate that the PNBT diode can potentially be used in high-efficiency rectification for energy harvesting, particularly in situations where there is ultralow input power. In addition, the hysteresis characteristics and the slight shift of the voltage at zero current are confirmed as specific characteristics of PNBT diodes.
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p channel super steep Subthreshold Slope pn body tied soi fet possibility of cmos
IEEE Electron Devices Technology and Manufacturing Conference, 2018Co-Authors: Takayuki Mori, Takahiro Yoshida, Jiro Ida, Yasuo AraiAbstract:We demonstrated a P-channel super steep Subthreshold Slope (SS) PN-Body Tied (PNBT) SOI FET, for the first time. We found out that the substrate bias is necessary for the appearance of the super steep SS on the P-channel PNBT. The device shows a super steep SS (<2mV/dec) keeping a low leakage current (< 1pA}/mum}) with an ultralow drain voltage (0.1V). It has also a very small hysteresis characteristic.
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gate controlled diode characteristics of super steep Subthreshold Slope pn body tied soi fet for high efficiency rf energy harvesting
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2017Co-Authors: Shun Momose, Takashi Horii, Takahiro Yoshida, Takayuki Mori, Jiro Ida, Kenji Itoh, Koichiro Ishibashi, Jumpei Iwata, Takahiro Furuta, Yasuo AraiAbstract:Gate controlled diode (GCD) characteristics with our newly proposed super steep Subthreshold Slope (SS) “PN-Body Tied SOI-FET” was shown, for the first time, compared with the conventional diodes. It shows the super steep characteristics, the low leakage current and the sharp On-characteristics even on the ultralow voltage range of 50mV. The simple circuit simulations also indicated that the GCD with “PN-Body Tied SOI-FET” will achieve the high efficiency rectification on the ultralow input power of the RF energy harvesting. Additionally, the slight shift of the voltage of the zero current was confirmed as a specific characteristics on this GCD.
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super steep Subthreshold Slope pn body tied soi fet s of ultra low drain voltage 0 1v with body bias below 1 0v
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2016Co-Authors: Takahiro Yoshida, Takashi Horii, Masao Okihara, Yasuo AraiAbstract:It was demonstrated that the body bias appearing the super steep Subthreshold Slope (SS) reduces from over 5V to below 1V on the PN-body tied SOIFET's which show the super steep SS with the ultralow drain voltage of 0.1V, when the impurity concentration of the N region on the body tied area is redesigned from the high concentration of the N+ to the low N−. The 3D device simulations also confirmed it and indicated that the optimum length of the N region exits on the different impurity concentration of it for appearing the super steep SS with the low body bias.
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super steep Subthreshold Slope pn body tied soi fet with ultra low drain voltage down to 0 1v
International Electron Devices Meeting, 2015Co-Authors: Takayuki Mori, Yousuke Kuramoto, Takashi Horii, Kazuma Takeda, Masao Okihara, Takahiro Yoshida, Hiroki Kasai, Yasuo AraiAbstract:We propose and demonstrate a super steep Subthreshold Slope (SS) new type SOI FET with a PN-body tied structure. It has a symmetry source and drain (S/D) structure. The device shows a super steep SS (<6mV/dec) over 3 decades of the drain current with an ultralow drain voltage down to 0.1V. It also shows a low leakage current (below 1pA/um), a good Id-Vd characteristic and a negligible hysteresis characteristic.
Jiro Ida - One of the best experts on this subject based on the ideXlab platform.
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precise transient mechanism of steep Subthreshold Slope pn body tied soi fet and proposal of a new structure for reducing leakage current upon turn off
International Conference on Simulation of Semiconductor Processes and Devices, 2019Co-Authors: Takayuki Mori, Jiro Ida, Hiroki Endo, Y AraiAbstract:In this study, the precise transient mechanism of the super-steep Subthreshold Slope PN-body-tied (PNBT) silicon on insulator field-effect transistor (SOI-FET) is clarified by using technology computer-aided design. We found out that the operation mechanism differs between the turn-on and turn-off. Additionally, a new PNBT SOI-FET structure with a second gate for the high-speed operation is proposed and we showed that the new structure can reduce the leakage current upon the turn-off.
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p channel and n channel super steep Subthreshold Slope pn body tied soi fet for ultralow power cmos
IEEE Journal of the Electron Devices Society, 2018Co-Authors: Takayuki Mori, Jiro IdaAbstract:In this paper, n-channel and p-channel super-steep Subthreshold Slope (SS) PN-body tied (PNBT) silicon on insulator field-effect transistors (SOI-FETs) are demonstrated. The PNBT structure has a symmetrical source and drain structure. The devices show super-steep SS ( $\mu$ m) and high on/off ratio (up to 6 decades) with low drain voltage (Vd = ± 0.1 V), good output characteristics, and threshold voltage controllability. The devices have a body current and a hysteresis characteristic; however, these can be suppressed under proper device conditions. The operation mechanism of the PNBT SOI-FET is clarified by simulation, and an inherent thyristor on the PNBT structure plays a significant role. Both the p-channel and n-channel PNBT SOI-FET characteristics are discussed, and it is indicated that an ultralow power complementary metal-oxide-semiconductor can be realized by the PNBT SOI-FET.
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first experimental confirmation of ultralow voltage rectification by super steep Subthreshold Slope pn body tied soi fet for high efficiency rf energy harvesting and ultralow voltage sensing
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2018Co-Authors: Shun Momose, Takayuki Mori, Jiro Ida, Kenji Itoh, Koichiro Ishibashi, Takuya Yamada, Y AraiAbstract:Rectification of the ultralow voltage signal, up to 10mV, was experimentally confirmed, for the first time, by our new device of the super steep Subthreshold Slope “PN-body Tied SOI-FET” (PNBT-FET). It comes from the surprisingly sharp turn-on characteristics of PNBT-FET, even with measuring on the ultra small voltage range. It is impossible with the conventional diodes, due to becoming the tangential line. Rectification up to 30 MHz was also confirmed with PNBT-FET. It is a good news for PNBT-FET because its conduction mechanism has the low speed concern. Those rectification demonstrations will be promising for small voltage rectification on RF energy harvesting and ultralow voltage sensing applications.
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diode characteristics of a super steep Subthreshold Slope pn body tied soi fet for energy harvesting applications
IEEE Journal of the Electron Devices Society, 2018Co-Authors: Takayuki Mori, Jiro Ida, Shun Momose, Kenji Itoh, Koichiro Ishibashi, Yasuo AraiAbstract:In this paper, the diode characteristics of our newly proposed super-steep Subthreshold Slope “PN-body tied (PNBT) silicon-on-insulator field-effect transistor” are presented, and compared with conventional diodes. We report that the device possesses super-steep characteristics, low leakage current, and sharp turn-on characteristics, even in the ultralow voltage range (50 mV). These indicate that the PNBT diode can potentially be used in high-efficiency rectification for energy harvesting, particularly in situations where there is ultralow input power. In addition, the hysteresis characteristics and the slight shift of the voltage at zero current are confirmed as specific characteristics of PNBT diodes.
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p channel super steep Subthreshold Slope pn body tied soi fet possibility of cmos
IEEE Electron Devices Technology and Manufacturing Conference, 2018Co-Authors: Takayuki Mori, Takahiro Yoshida, Jiro Ida, Yasuo AraiAbstract:We demonstrated a P-channel super steep Subthreshold Slope (SS) PN-Body Tied (PNBT) SOI FET, for the first time. We found out that the substrate bias is necessary for the appearance of the super steep SS on the P-channel PNBT. The device shows a super steep SS (<2mV/dec) keeping a low leakage current (< 1pA}/mum}) with an ultralow drain voltage (0.1V). It has also a very small hysteresis characteristic.
Seung Ki Joo - One of the best experts on this subject based on the ideXlab platform.
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Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor
Scientific Reports, 2016Co-Authors: Jae Hyo Park, Gil Su Jang, Hyung Yoon Kim, Ki Hwan Seok, Hee Jae Chae, Sol Kyu Lee, Seung Ki JooAbstract:Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q Subthreshold Slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O_3 (PZT)/ZrTiO_4 (ZTO) gate dielectrics has been demonstrated. The sub-kT/q SS was observed in the weak inversion region at −0.5 V showing ultra-low operating voltage with the highest mobility (250.5 cm^2/Vsec) reported so far. In addition, the reliability of DC negative bias stress, hot carrier stress and self-heating stress in LTPS-TFT with negative capacitance was investigated for the first time. It was found that the self-heating stress showed accelerated SS degradation due to the PZT Curie temperature.
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sub kt q Subthreshold Slope p metal oxide semiconductor field effect transistors with single grained pb zr ti o3 featuring a highly reliable negative capacitance
Applied Physics Letters, 2016Co-Authors: Jae Hyo Park, Seung Ki JooAbstract:A reliable on/off switching with an sub-kT/q Subthreshold Slope (38 mV/dec at room temperature) is experimentally demonstrated with using selectively nucleated laterally crystallized single-grain Pb(Zr,Ti)O3 (PZT) ferroelectric and ZrTiO4 paraelectric thin-film. The combination of ferroelectric and paraelectric thin-film is enabled to form a negative capacitance (NC) at the weak inversion region. However, the PZT grain-boundary easily degrades the NC properties after switching the on/off more than 108 times. It is found that the polarization of PZT is diminished from the path of grain-boundary. Here, we effectively suppress the degradation of NC MOS-FET which did not showed any fatigue even after 108 on/off switching.At the request of the authors this article is retracted due to duplication of figures and significant overlap with other publications by the authors and because of concerns about the accuracy of the description of the devices and materials from which the reported results were obtained. The au...
