The Experts below are selected from a list of 567 Experts worldwide ranked by ideXlab platform
Iman Madadi - One of the best experts on this subject based on the ideXlab platform.
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a fully integrated discrete time Superheterodyne Receiver
IEEE Transactions on Very Large Scale Integration Systems, 2017Co-Authors: Massoud Tohidian, Iman Madadi, Robert Bogdan StaszewskiAbstract:The zero/low intermediate frequency (IF) Receiver (RX) architecture has enabled full CMOS integration. As the technology scales and wireless standards become ever more challenging, the issues related to time-varying dc offsets, the second-order nonlinearity, and flicker noise become more critical. In this paper, we propose a new architecture of a Superheterodyne RX that attempts to avoid such issues. By exploiting discrete-time (DT) operation and using only switches, capacitors, and inverter-based gm-stages as building blocks, the architecture becomes amenable to further scaling. Full integration is achieved by employing a cascade of four complex-valued passive switched-cap-based bandpass filters sampled at $4\times $ of the local oscillator rate that perform IF image rejection. Channel selection is achieved through an equivalent of the seventh-order filtering. A new twofold noise-canceling low-noise transconductance amplifier is proposed. Frequency domain analysis of the RX is presented by the proposed DT model. The RX is wideband and covers 0.4–2.9 GHz with a noise figure of 2.9–4 dB. It is implemented in 65-nm CMOS and consumes 48–79 mW.
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a high iip2 saw less Superheterodyne Receiver with multistage harmonic rejection
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Iman Madadi, Massoud Tohidian, Koen Cornelissens, Patrick Vandenameele, Robert Bogdan StaszewskiAbstract:In this paper, we propose and demonstrate the first fully integrated surface acoustic wave (SAW)-less Superheterodyne Receiver (RX) for 4G cellular applications. The RX operates in discrete-time domain and introduces various innovations to simultaneously improve noise and linearity performance while reducing power consumption: a highly linear wideband noise-canceling low-noise transconductance amplifier (LNTA), a blocker-resilient octal charge-sharing bandpass filter, and a cascaded harmonic rejection circuitry. The RX is implemented in 28-nm CMOS and it does not require any calibration. It features NF of 2.1–2.6 dB, an immeasurably high input second intercept point for closely-spaced or modulated interferers, and input third intercept point of 8–14 dBm, while drawing only 22–40 mW in various operating modes.
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fully integrated saw less discrete time Superheterodyne Receiver
2015Co-Authors: Iman MadadiAbstract:There are nowadays strong business and technical demands to integrate radio- frequency (RF) Receivers (RX) into a complete system-on-chip (SoC) realized in scaled digital processes technology. As a consequence, the RF circuitry has to function well in face of reduced power supply ( V DD ) while the CMOS device threshold voltage ( V th ) stays almost constant. Therefore, a conventional or continuous-time (CT) approach could not be efficiently utilized to design and implement the SoC, whereas a discrete-time (DT) approach offers the advantage for RF building blocks to operate properly in a smaller headroom. Furthermore, in finer CMOS technologies, transit frequency ( f T ) increases while CT RF building blocks do not benefit except for low-noise amplifiers (LNA). However, the performance of DT RF building blocks improves because of the higher sampling frequency ( f s ), lower power supply, and sharper clock edges provided by technology scaling. Nowadays, most integrated RF Receivers are zero-IF (ZIF) because of well- known advantages such as less complicated architecture and easy channel-selection integration. They require many external duplexers, surface acoustic wave (SAW) filters, and switches, typically one per band, to attenuate out-of-band (OB) blockers. However, there are many issues associated with ZIF Receivers such as time-variant DC offsets, sensitivity to 1 /f (flicker) noise, large in-band LO leakage, and second- order nonlinearity. For solving those issues, high-performance cellular SAW-less ZIF Receivers now require extensive calibration efforts. For example, an intensive input 2 nd -order intercept point (IIP2) calibration must be simultaneously operated in the background with DC offset and harmonic rejection (HR) calibrations. Also, this calibration is susceptible to many factors such as variations in power supply, process corner, temperature, RF blocker frequency, local oscillator (LO) frequency, LO power, and channel frequency. On the other hand, a Superheterodyne architecture pushes the IF frequency much higher so that the aforementioned problems are eliminated. Despite the advantages, the Superheterodyne radios have not been utilized in cellular Receivers simply because of the difficulty with integration of a high quality (Q)-factor band-pass filter (BPF) for image rejection in CMOS using CT circuitry. In this thesis, a new class of filters, i.e., charge-sharing (CS), is discussed that is being invented and developed to be utilized in not only Superheterodyne but also in ZIF Receivers. The proposed filter not only filters OB-blockers but also rejects interferers at the harmonic of LO frequency which is an extraordinary advantage especially for SAW-less Receivers when there is no external filtering prior to the Receiver input. Using these techniques, for the first-time ever, the Superheterodyne Receiver is proposed that meets the specification for SAW-less Receivers. Chapter 1 briefly provides an overview of the blocks inside conventional RF radio transceivers. It mentions that there is a tendency in RF transceivers to support many of the multi-mode/multi-band communication standards such as Fourth Generation (4G) cellular application, Bluetooth, and Wi-Fi in one SoC. Also, the organization of the thesis has been described in details in this chapter. Chapter 2 establishes a common background for this thesis. Furthermore, it provides the background information for different sampling modes of operation such as subsampling (1x), half-rate sampling (2x) and full-rate sampling (4x) together with their frequency translations. Also, the technical mathematic background related to nonlinearity is briefly consolidated in this chapter. Chapter 3 discusses the first implemented DT Superheterodyne Receiver that utilizes the full-rate (4x) sampling mode of operation to solve a number of issues related to previous DT Receivers. Chapter 4 explores performance capabilities and limitations of the proposed CS-BPF. A complex quadrature charge-sharing technique is proposed to implement a CS-BPF with a programmable bandwidth. It operates at the full sampling rate (4x), which was described in Chapter 2. Also, the complete noise analysis of the proposed CS-BPF is investigated. Additionally, the CT model of the CS-BPF is presented, and the filtering characteristic of proposed model has excellent agreement with the simulation result of the DT circuit. Finally, the implemented chip is fabricated in 65 nm CMOS, and the measured results are compared with simulations. Chapter 5 explores the possibility of creating a high quality (Q)-factor BPF at a very high IF because the CS-BPF proposed in Chapter 4 does not provide adequate selectivity. As a result, a highly reconfigurable Superheterodyne RX is proposed that employs a 3rd-order complex IQ CS-BPF for image rejection and 1st-order feedback based RF-BPF for channel selection filtering. The proposed RX is the first attempt to achieve high-Q factor BPF at a very high-IF without replicas and images. Furthermore, the chip is fabricated in 65 nm CMOS technology, and the simulated results are completely verified by the measured results. Chapter 6 proposes and demonstrates the first-ever fully integrated SAW-less Superheterodyne Receiver for 4G cellular applications. The low-power DT RX introduces various innovations that simultaneously improve noise and linearity performance: a highly linear wideband noise-canceling LNTA, a blocker-resilient octal CS-BPF, and a cascaded harmonic rejection circuitry. The chip is fabricated in 28 nm CMOS technology, the characteristics of the fabricated chip are extensively measured, and the results are compared with the simulations. Chapter 7 draws the conclusions of this thesis work and provides recommendations for future research.
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analysis and design of i q charge sharing band pass filter for Superheterodyne Receivers
IEEE Transactions on Circuits and Systems, 2015Co-Authors: Iman Madadi, Massoud Tohidian, Robert Bogdan StaszewskiAbstract:A complex quadrature charge-sharing (CS) technique is proposed to implement a discrete-time band-pass filter (BPF) with a programmable bandwidth of 20–100 MHz. The BPF is part of a cellular Superheterodyne Receiver and completely determines the Receiver frequency selectivity. It operates at the full sampling rate of up to 5.2 GHz corresponding to the 1.2 GHz RF input frequency, thus making it free from any aliasing or replicas in its transfer function. Furthermore, the advantage of CS-BPF over other band-pass filters such as N-path, active-RC, ${\rm G}_{m}$ - ${\rm C}$ , and biquad is described. A mathematical noise analysis of the CS-BPF and the comparison of simulations and calculations are presented. The entire 65 nm CMOS Receiver, which does not include a front-end LNTA for test reasons, achieves a total gain of 35 dB, IRN of $1.5\ nV/\sqrt{Hz}$ , out-of-band IIP3 of $+$ 10 dBm. It consumes 24 mA at 1.2 V power supply.
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a tdd fdd saw less Superheterodyne Receiver with blocker resilient band pass filter and multi stage hr in 28nm cmos
Symposium on VLSI Circuits, 2015Co-Authors: Iman Madadi, Massoud Tohidian, Koen Cornelissens, Patrick Vandenameele, Bogdan R StaszewskiAbstract:A SAW-less discrete-time Superheterodyne Receiver (RX) with multi-stage harmonic rejection in 28nm CMOS, featuring highly linear LNTA, employs a novel blocker-resilient octal charge-sharing band-pass filter to achieve low power consumption. The RX features NF of 2.1 to 2.6 dB, and IIP3 of 8 to 14 dBm, while drawing only 24 to 37 mW in different operating modes.
Robert Bogdan Staszewski - One of the best experts on this subject based on the ideXlab platform.
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a fully integrated discrete time Superheterodyne Receiver
IEEE Transactions on Very Large Scale Integration Systems, 2017Co-Authors: Massoud Tohidian, Iman Madadi, Robert Bogdan StaszewskiAbstract:The zero/low intermediate frequency (IF) Receiver (RX) architecture has enabled full CMOS integration. As the technology scales and wireless standards become ever more challenging, the issues related to time-varying dc offsets, the second-order nonlinearity, and flicker noise become more critical. In this paper, we propose a new architecture of a Superheterodyne RX that attempts to avoid such issues. By exploiting discrete-time (DT) operation and using only switches, capacitors, and inverter-based gm-stages as building blocks, the architecture becomes amenable to further scaling. Full integration is achieved by employing a cascade of four complex-valued passive switched-cap-based bandpass filters sampled at $4\times $ of the local oscillator rate that perform IF image rejection. Channel selection is achieved through an equivalent of the seventh-order filtering. A new twofold noise-canceling low-noise transconductance amplifier is proposed. Frequency domain analysis of the RX is presented by the proposed DT model. The RX is wideband and covers 0.4–2.9 GHz with a noise figure of 2.9–4 dB. It is implemented in 65-nm CMOS and consumes 48–79 mW.
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a high iip2 saw less Superheterodyne Receiver with multistage harmonic rejection
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Iman Madadi, Massoud Tohidian, Koen Cornelissens, Patrick Vandenameele, Robert Bogdan StaszewskiAbstract:In this paper, we propose and demonstrate the first fully integrated surface acoustic wave (SAW)-less Superheterodyne Receiver (RX) for 4G cellular applications. The RX operates in discrete-time domain and introduces various innovations to simultaneously improve noise and linearity performance while reducing power consumption: a highly linear wideband noise-canceling low-noise transconductance amplifier (LNTA), a blocker-resilient octal charge-sharing bandpass filter, and a cascaded harmonic rejection circuitry. The RX is implemented in 28-nm CMOS and it does not require any calibration. It features NF of 2.1–2.6 dB, an immeasurably high input second intercept point for closely-spaced or modulated interferers, and input third intercept point of 8–14 dBm, while drawing only 22–40 mW in various operating modes.
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analysis and design of i q charge sharing band pass filter for Superheterodyne Receivers
IEEE Transactions on Circuits and Systems, 2015Co-Authors: Iman Madadi, Massoud Tohidian, Robert Bogdan StaszewskiAbstract:A complex quadrature charge-sharing (CS) technique is proposed to implement a discrete-time band-pass filter (BPF) with a programmable bandwidth of 20–100 MHz. The BPF is part of a cellular Superheterodyne Receiver and completely determines the Receiver frequency selectivity. It operates at the full sampling rate of up to 5.2 GHz corresponding to the 1.2 GHz RF input frequency, thus making it free from any aliasing or replicas in its transfer function. Furthermore, the advantage of CS-BPF over other band-pass filters such as N-path, active-RC, ${\rm G}_{m}$ - ${\rm C}$ , and biquad is described. A mathematical noise analysis of the CS-BPF and the comparison of simulations and calculations are presented. The entire 65 nm CMOS Receiver, which does not include a front-end LNTA for test reasons, achieves a total gain of 35 dB, IRN of $1.5\ nV/\sqrt{Hz}$ , out-of-band IIP3 of $+$ 10 dBm. It consumes 24 mA at 1.2 V power supply.
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3 8 a fully integrated highly reconfigurable discrete time Superheterodyne Receiver
International Solid-State Circuits Conference, 2014Co-Authors: Massoud Tohidian, Iman Madadi, Robert Bogdan StaszewskiAbstract:Since the invention of radio, Superheterodyne has been the architecture of choice for Receivers (RX). Thanks to its high intermediate-frequency (IF), the problems related to flicker noise, time-varying dc offsets, in-band LO leakage and sensitivity to 2nd-order intermodulation are simply avoided. Unfortunately, the high IF requires high-quality-factor (Q) band-pass filters for image rejection, which cannot be easily integrated in CMOS. This forced the CMOS Receivers to migrate to zero (or low) IF and suffer from the abovementioned problems. Recently, there have been attempts to revisit the high IF operation by exploiting N-path filtering [1] and a combination of a discrete-time (DT) band-pass charge-sharing filtering with feedback filtering [2]. Here, we propose a Superheterodyne RX architecture with full DT operation using only gm stages, switches and capacitors. The transfer function is accurate and controlled by the clock frequency and precise capacitor ratios.
Massoud Tohidian - One of the best experts on this subject based on the ideXlab platform.
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a fully integrated discrete time Superheterodyne Receiver
IEEE Transactions on Very Large Scale Integration Systems, 2017Co-Authors: Massoud Tohidian, Iman Madadi, Robert Bogdan StaszewskiAbstract:The zero/low intermediate frequency (IF) Receiver (RX) architecture has enabled full CMOS integration. As the technology scales and wireless standards become ever more challenging, the issues related to time-varying dc offsets, the second-order nonlinearity, and flicker noise become more critical. In this paper, we propose a new architecture of a Superheterodyne RX that attempts to avoid such issues. By exploiting discrete-time (DT) operation and using only switches, capacitors, and inverter-based gm-stages as building blocks, the architecture becomes amenable to further scaling. Full integration is achieved by employing a cascade of four complex-valued passive switched-cap-based bandpass filters sampled at $4\times $ of the local oscillator rate that perform IF image rejection. Channel selection is achieved through an equivalent of the seventh-order filtering. A new twofold noise-canceling low-noise transconductance amplifier is proposed. Frequency domain analysis of the RX is presented by the proposed DT model. The RX is wideband and covers 0.4–2.9 GHz with a noise figure of 2.9–4 dB. It is implemented in 65-nm CMOS and consumes 48–79 mW.
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a high iip2 saw less Superheterodyne Receiver with multistage harmonic rejection
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Iman Madadi, Massoud Tohidian, Koen Cornelissens, Patrick Vandenameele, Robert Bogdan StaszewskiAbstract:In this paper, we propose and demonstrate the first fully integrated surface acoustic wave (SAW)-less Superheterodyne Receiver (RX) for 4G cellular applications. The RX operates in discrete-time domain and introduces various innovations to simultaneously improve noise and linearity performance while reducing power consumption: a highly linear wideband noise-canceling low-noise transconductance amplifier (LNTA), a blocker-resilient octal charge-sharing bandpass filter, and a cascaded harmonic rejection circuitry. The RX is implemented in 28-nm CMOS and it does not require any calibration. It features NF of 2.1–2.6 dB, an immeasurably high input second intercept point for closely-spaced or modulated interferers, and input third intercept point of 8–14 dBm, while drawing only 22–40 mW in various operating modes.
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fully integrated discrete time Superheterodyne Receiver in nano scale cmos
2015Co-Authors: Massoud TohidianAbstract:In a radio-frequency (RF) system-on-chip (SoC), a digital baseband/application processor, which occupies most of the silicon area, determines the SoC fabrication process technology and voltage supply. The rest of the circuitry, including RF front-end and frequency synthesizer, must then adopt the chosen process technology, i.e., presently low-voltage deep nano-scale CMOS. To design a fully integrated power/area efficient Receiver in this respect, new RF/analog techniques are required to be able to function well at the reduced voltage headroom. In addition, new oscillator structures need to be developed that can work at low supply voltages and in face of poor quality current sources while providing high spectral purity. On the other hand, conventional RF/analog designs have not benefited significantly from CMOS scaling, which continually reduces transistor cost and improves digital performance. Here in this thesis, traditional continuous-time (CT) analog components, such as opamps, are avoided and, instead, most of signal processing and filtering is done using passive switched-capacitor circuits in discrete-time (DT) domain. In this way, the Receiver front-end becomes process scalable similar to digital circuits enjoying performance and cost improvements with each process scaling node. In the first part of this dissertation, principles, design and implementation of a fully integrated DT Superheterodyne Receiver frontend are described. To start with, the optimal sampling scheme in a high-intermediate frequency (IF) Receiver architecture is explained. It is followed by sequentially introducing all the constituent circuits. A novel DT high-order low-pass filter is proposed to be used at the Receiver baseband. This filter has an exceptionally low noise and high linearity. Deep analysis, verified by test-chip measurements, is presented. Next, a very high 156 Summary sampling rate DT bandpass filter (BPF) using I/Q charge sharing is proposed and analyzed. Then, a novel wideband noise-cancelling LNTA is proposed with a two-fold noise cancellation technique. Finally, a fully integrated DT Superheterodyne Receiver is proposed with explanations to its DT model, frequency translations, and image rejection mechanisms. The whole idea, design and analyses are successfully verified by a 65-nm CMOS test chip. The implemented Receiver has an exceptional high uncalibrated IIP2 of +90 dBm. In the second part of this dissertation, design and implementations of low-voltage fully integrated oscillators in nano-scale CMOS are discussed. First, a high-swing class-C oscillator is proposed that efficiently uses the drastically reduced supply voltage in nano-scale CMOS. Measurement results of a low-power low-voltage test chip in 90-nm CMOS shows phase noise figure-of-merit as high as 192 dBc/Hz from a 0.6V power supply. The idea of the high-swing class-C oscillator is extended to an ultra-low phase noise dual-core oscillator implemented in 65nm CMOS. This oscillator is the first-ever fully integrated design that meets phase noise requirements of a GSM basestation standard in a bulk CMOS technology. Next, another novel low-voltage oscillator topology is proposed that uses a series-LC tank ring structure. Its realization in 40-nm CMOS targets low silicon area using low-Q inductors. It exhibits 7–20 dB better phase noise than other state-of-the-art low area oscillators.
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analysis and design of i q charge sharing band pass filter for Superheterodyne Receivers
IEEE Transactions on Circuits and Systems, 2015Co-Authors: Iman Madadi, Massoud Tohidian, Robert Bogdan StaszewskiAbstract:A complex quadrature charge-sharing (CS) technique is proposed to implement a discrete-time band-pass filter (BPF) with a programmable bandwidth of 20–100 MHz. The BPF is part of a cellular Superheterodyne Receiver and completely determines the Receiver frequency selectivity. It operates at the full sampling rate of up to 5.2 GHz corresponding to the 1.2 GHz RF input frequency, thus making it free from any aliasing or replicas in its transfer function. Furthermore, the advantage of CS-BPF over other band-pass filters such as N-path, active-RC, ${\rm G}_{m}$ - ${\rm C}$ , and biquad is described. A mathematical noise analysis of the CS-BPF and the comparison of simulations and calculations are presented. The entire 65 nm CMOS Receiver, which does not include a front-end LNTA for test reasons, achieves a total gain of 35 dB, IRN of $1.5\ nV/\sqrt{Hz}$ , out-of-band IIP3 of $+$ 10 dBm. It consumes 24 mA at 1.2 V power supply.
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a tdd fdd saw less Superheterodyne Receiver with blocker resilient band pass filter and multi stage hr in 28nm cmos
Symposium on VLSI Circuits, 2015Co-Authors: Iman Madadi, Massoud Tohidian, Koen Cornelissens, Patrick Vandenameele, Bogdan R StaszewskiAbstract:A SAW-less discrete-time Superheterodyne Receiver (RX) with multi-stage harmonic rejection in 28nm CMOS, featuring highly linear LNTA, employs a novel blocker-resilient octal charge-sharing band-pass filter to achieve low power consumption. The RX features NF of 2.1 to 2.6 dB, and IIP3 of 8 to 14 dBm, while drawing only 24 to 37 mW in different operating modes.
Scott K Reynolds - One of the best experts on this subject based on the ideXlab platform.
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second generation 60 ghz transceiver chipset supporting multiple modulations at gb s data rates invited
Bipolar BiCMOS Circuits and Technology Meeting, 2007Co-Authors: Scott K Reynolds, Brian Floyd, T Beukema, Alberto Valdesgarcia, Brian P Gaucher, Duixian Liu, N Hoivik, Bradley A OrnerAbstract:A feature-rich second-generation 60-GHz transceiver chipset is introduced. It integrates dual-conversion Superheterodyne Receiver and transmitter chains, a sub-integer frequency synthesizer, full programmability from a digital interface, modulator and demodulator circuits to support analog modulations (e.g. MSK, BPSK), as well as a universal I&Q interface for digital modulation formats (e.g. OFDM). Achieved performance includes 6-dB Receiver noise figure and 12 dBm transmitter output ldB compression point. Wireless link experiments with different modulation formats for 2-Gb/s real-time uncompressed HDTV transmission are discussed. Additionally, recent millimeter-wave package and antenna developments are summarized and a 60GHz silicon micromachined antenna is presented.
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a silicon 60 ghz Receiver and transmitter chipset for broadband communications
IEEE Journal of Solid-state Circuits, 2006Co-Authors: Scott K Reynolds, Brian Floyd, Ullrich R Pfeiffer, T Beukema, Janusz Grzyb, C Haymes, Brian P Gaucher, M SoyuerAbstract:A 0.13-mum SiGe BiCMOS double-conversion Superheterodyne Receiver and transmitter chipset for data communications in the 60-GHz band is presented. The Receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P1dB of 10 to 12dBm, Psat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated
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a 60 ghz Superheterodyne downconversion mixer in silicon germanium bipolar technology
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Scott K ReynoldsAbstract:A single-balanced Gilbert mixer intended for use in a Superheterodyne Receiver in the 57-64-GHz ISM band has been fabricated in SiGe bipolar technology. Using an output IF in the range of 8.3-9.1 GHz, the mixer achieves a voltage conversion gain >9 dB and an upper single-sideband noise figure <13 dB, with mixer core current consumption of 3.2 mA at 2.7 V. Total test-site current consumption, including an output buffer, is 19.2 mA.
Larry Turner - One of the best experts on this subject based on the ideXlab platform.
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Induction-Motor Rotor Temperature Estimation Using Superheterodyne Receivers
IEEE Transactions on Industry Applications, 2012Co-Authors: Zhi Gao, Roy S. Colby, Larry TurnerAbstract:A rotor temperature estimator is proposed in this paper for grid-connected squirrel-cage induction motors during dynamic or steady-state operations. The method utilizes a pipelined architecture with two Superheterodyne Receivers that operate on a common complex current vector input. The first Superheterodyne Receiver detects motor speed by extracting an instantaneous rotor-slot-harmonic frequency from the complex current vector. The second Superheterodyne Receiver extracts a complex fundamental current vector from the same complex current vector. Given a few known motor parameters and a complex voltage vector, a model-reference adaptive system then produces an estimate of the rotor time constant from the Superheterodyne Receivers' outputs. Finally, the rotor temperature is derived from the estimated rotor time constant via a correlation between the rotor temperature and its resistance. Experimental results demonstrate that the proposed method is capable of estimating induction-motor rotor temperature on a sample-by-sample basis without using temperature or speed sensors.
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Induction motor rotor temperature estimation using Superheterodyne Receivers
2011 IEEE Energy Conversion Congress and Exposition, 2011Co-Authors: Zhi Gao, Roy S. Colby, Larry TurnerAbstract:A rotor temperature estimator is proposed in this paper for line-connected squirrel-cage induction motors during dynamic or steady-state operations. The method utilizes a pipelined architecture with two Superheterodyne Receivers that operate in parallel on a complex current vector. The first Superheterodyne Receiver detects motor speed by extracting an instantaneous rotor slot harmonic frequency from the complex current vector. The second Superheterodyne Receiver extracts a complex fundamental current vector from the same complex current vector. A model-reference adaptive system then produces an estimate of the rotor time constant from the Superheterodyne Receivers' outputs, plus a complex voltage vector and a few motor parameters. Finally, the rotor temperature is derived from the estimated rotor time constant via a correlation between the rotor temperature and its resistance. Experimental results demonstrate that the proposed method is capable of estimating induction motor rotor temperature on a sample-by-sample basis without using temperature or speed sensors.