The Experts below are selected from a list of 15495 Experts worldwide ranked by ideXlab platform
Yuwei Yang - One of the best experts on this subject based on the ideXlab platform.
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temperature aware dynamic frequency and Voltage scaling for reliability and yield enhancement
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Yuwei Yang, Katherine Shumin LiAbstract:A novel oscillation-based on-chip thermal sensing architecture for dynamically adjusting Supply Voltage and clock frequency in System-on-Chip (SoC) is proposed. It is shown that the oscillation frequency of a ring oscillator reduces linearly as the temperature rises, and thus provides a good on-chip temperature sensing mechanism. An efficient Dynamic Frequency-to-Voltage Scaling (DF2VS) algorithm is proposed to dynamically adjust Supply Voltage according to the oscillation frequencies of the ring oscillators distributed in SoC so that thermal sensing can be carried at all potential hot spots. An on-chip Dynamic Voltage Scaling or Dynamic Voltage and Frequency Scaling (DVS or DVFS) monitor selects the Supply Voltage Level and clock frequency according to the outputs of all thermal sensors. Experimental results on SoC benchmark circuits show the effectiveness of the algorithm that a 10% reduction in Supply Voltage alone can achieve about 20% power reduction (DVS scheme), and nearly 50% reduction in power is achievable if the clock frequency is also scaled down (DVFS scheme). The chip temperature is reduced accordingly.
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temperature aware dynamic frequency and Voltage scaling for reliability and yield enhancement
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Yuwei YangAbstract:A novel oscillation-based on-chip thermal sensing architecture for dynamically adjusting Supply Voltage and clock frequency in System-on-Chip (SoC) is proposed. It is shown that the oscillation frequency of a ring oscillator reduces linearly as the temperature rises, and thus provides a good on-chip temperature sensing mechanism. An efficient Dynamic Frequency-to-Voltage Scaling (DF2VS) algorithm is proposed to dynamically adjust Supply Voltage according to the oscillation frequencies of the ring oscillators distributed in SoC so that thermal sensing can be carried at all potential hot spots. An on-chip Dynamic Voltage Scaling or Dynamic Voltage and Frequency Scaling (DVS or DVFS) monitor selects the Supply Voltage Level and clock frequency according to the outputs of all thermal sensors. Experimental results on SoC benchmark circuits show the effectiveness of the algorithm that a 10% reduction in Supply Voltage alone can achieve about 20% power reduction (DVS scheme), and nearly 50% reduction in power is achievable if the clock frequency is also scaled down (DVFS scheme). The chip temperature is reduced accordingly.
Katherine Shumin Li - One of the best experts on this subject based on the ideXlab platform.
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temperature aware dynamic frequency and Voltage scaling for reliability and yield enhancement
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Yuwei Yang, Katherine Shumin LiAbstract:A novel oscillation-based on-chip thermal sensing architecture for dynamically adjusting Supply Voltage and clock frequency in System-on-Chip (SoC) is proposed. It is shown that the oscillation frequency of a ring oscillator reduces linearly as the temperature rises, and thus provides a good on-chip temperature sensing mechanism. An efficient Dynamic Frequency-to-Voltage Scaling (DF2VS) algorithm is proposed to dynamically adjust Supply Voltage according to the oscillation frequencies of the ring oscillators distributed in SoC so that thermal sensing can be carried at all potential hot spots. An on-chip Dynamic Voltage Scaling or Dynamic Voltage and Frequency Scaling (DVS or DVFS) monitor selects the Supply Voltage Level and clock frequency according to the outputs of all thermal sensors. Experimental results on SoC benchmark circuits show the effectiveness of the algorithm that a 10% reduction in Supply Voltage alone can achieve about 20% power reduction (DVS scheme), and nearly 50% reduction in power is achievable if the clock frequency is also scaled down (DVFS scheme). The chip temperature is reduced accordingly.
Massoud Pedram - One of the best experts on this subject based on the ideXlab platform.
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tip a temperature effect inversion aware ultra low power system on chip platform
International Symposium on Low Power Electronics and Design, 2019Co-Authors: Kyuseung Han, Woojoo Lee, Jaejin Lee, Sukho Lee, Massoud PedramAbstract:Researchers have been trying to exploit the temperature effect inversion (TEI) phenomenon to improve energy efficiency of system-on-chip (SoC) designs without sacrificing its performance. However, TEI-aware low power methods have a critical limitation in that they can only be applied to components within the SoC that do not contain long (global) wires. This is because wire delays continue to increase with rising temperatures irrespective of the operating Supply Voltage Level, which tends to cancel out positive effects of the TEI phenomenon in SoCs. To tackle this limitation and thoroughly utilize the TEI-aware methods, this paper presents new TEI-inspired SoC platform (called TIP), which relies on network-on-chip architecture (called µNoC) to realize system interconnects. The µNoC successfully reduces the total number and length of global wires. By fabricating a TIP prototyping chip in Samsung 28nm FD-SOI technology, we verify the effectiveness of TIP. Extensive post-fabrication measurements demonstrate that the chip while continuing to operate at a target 50MHz clock frequency can lower its Supply Voltage from 0.54V to 0.48V at 25°C and to 0.44V at 80°C, which results in up to 35% power saving.
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tei noc optimizing ultralow power nocs exploiting the temperature effect inversion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018Co-Authors: Kyuseung Han, Woojoo Lee, Jaejin Lee, Jinho Lee, Massoud PedramAbstract:The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern of system-on-chip designers. Ultralow power (ULP) very large-scale integration circuits have been receiving considerable interest from both academia and industry as the best-suited techniques for IoT devices, which can take full advantage of power-saving that Voltage scaling potentially achieves. Consequently, research on ULP designs has begun to yield tangible outcomes, namely ULP circuits. However, little attention has been paid to ULP network-on-chip (NoC), although the NoC is an essential of the ULP chips, and its power consumption accounts for a significant portion of the total power. This paper focuses on ULP NoCs, and presents a new power management method that exploits delay versus temperature characteristics of ULP circuits. Recent studies on ULP circuits show that delay versus temperature characteristics are fundamentally different from normal circuits, i.e., the delay of the ULP circuits implemented in state-of-the-art bulk CMOS operating at low Supply Voltages or in FinFET technologies decreases with increasing temperature, a phenomenon known as the temperature effect inversion (TEI). Starting with an intuition that at a certain temperature point, power savings without performance penalty can be achieved by increasing the router frequency to create the opportunity to turn off some routers in ULP NoCs, or by decreasing the NoC Supply Voltage Level, an optimization method is presented to maximize the power savings with minor performance penalty. To validate the proposed method, a concrete ULP NoC simulator, TEI-Noxim, has been developed. Experimental results demonstrate that TEI-aware NoC achieves an average of 36.0% power reduction over 21 applications.
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energy minimization using multiple Supply Voltages
IEEE Transactions on Very Large Scale Integration Systems, 1997Co-Authors: Juiming Chang, Massoud PedramAbstract:We present a dynamic programming technique for solving the multiple Supply Voltage scheduling problem in both nonpipelined and functionally pipelined data-paths. The scheduling problem refers to the assignment of a Supply Voltage Level (selected from a fixed and known number of Voltage Levels) to each operation in a data flow graph so as to minimize the average energy consumption for given computation time or throughput constraints or both. The energy model is accurate and accounts for the input pattern dependencies, re-convergent fanout induced dependencies, and the energy cost of Level shifters. Experimental results show that using three Supply Voltage Levels on a number of standard benchmarks, an average energy saving of 40.19% (with a computation time constraint of 1.5 times the critical path delay) can be obtained compared to using a single Supply Voltage Level.
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energy minimization using multiple Supply Voltages
International Symposium on Low Power Electronics and Design, 1996Co-Authors: Juiming Chang, Massoud PedramAbstract:We present a dynamic programming technique for solving the multiple Supply Voltage scheduling problem in both non-pipelined and functionally pipelined data-paths. The scheduling problem refers to the assignment of a Supply Voltage Level to each operation in a data flow graph so as to minimize the average energy consumption for given computation time or throughput constraints or both. The energy model is accurate and accounts for the input pattern dependencies, re-convergent fanout induced dependencies, and the energy cost of Level shifters. Experimental results show that using four Supply Voltage Levels on a number of standard benchmarks, an average energy saving of 53% (with a computation time constraint of 1.5 times the critical path delay) can be obtained compared to using one fixed Supply Voltage Level.
Stelzer J.e. - One of the best experts on this subject based on the ideXlab platform.
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Low stored energy 100 kV regulator for ion sources at LANSCE
Los Alamos National Laboratory, 1998Co-Authors: Jacobson E.g., Haffner R.l., Ingalls W.b., Meyer B.j., Stelzer J.e.Abstract:To minimize accelerating column damage caused by uncontrolled energy release during arc-downs, it is desirable to minimize the available stored electrical energy. For the Los Alamos Neutron Science Center (LANSCE) H{sup {minus}} ion sources, the stored energy includes, in addition to the charge in the power Supply output capacitance, the charge on the electronics racks. They are supported and insulated from ground by PVC pipe and have a capacitance to ground of approximately 900 pf. In 1988 (LANSCE) personnel designed a high-Voltage current source using a low-stored-energy power Supply and planar triode with the goal of eliminating uncontrolled release of charge stored in the power Supply. Construction and testing were performed intermittently as resources permitted until 1993. When work on the Short Pulse Spallation Source (SPSS) started on the LANSCE Ion Source Test Stand (ISTS) it was recognized that a higher current power Supply would be needed and work resumed on the regulator circuitry. A 120 kV power Supply having low output capacitance, and a planar triode have been used to Supply 40 mA, 120 Hz, 12% duty-factor current for the ISTS beam. The triode`s cathode current is controlled by circuitry operating both at power-Supply Voltage Level and at ground Level via a fiber optic link. Voltage droop is approximately 600 V during the 1 ms beam pulse. The authors present the status of the regulator and its special challenges
J. E. Stelzer - One of the best experts on this subject based on the ideXlab platform.
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LOW-STORED-ENERGY 100-kV REGULATOR FOR ION SOURCES AT LANSCE *
2015Co-Authors: E. G. Jacobson, R. L. Haffner, W. B. Ingalls, B. J. Meyer, J. E. StelzerAbstract:At Los Alamos Neutron Science Center (LANSCE), as elsewhere, it is desirable to minimize the available stored electrical energy for the H- ion sources to minimize accelerating column damage caused by uncontrolled energy release during arc-downs. The stored energy includes, in addition to the charge in the power Supply output capacitance, the charge on the electronics racks. The racks are supported and insulated from ground by PVC pipe and have a capacitance to ground of approximately 900 pf. In 1988 LANSCE personnel designed a high-Voltage current source using a low-stored-energy power Supply and planar triode with the goal of eliminating uncontrolled release of charge stored in the power Supply. Construction and testing were performed intermittently as resources permitted until 1993. When work on the Short-Pulse Spallation Source (SPSS) [1] started on the LANSCE Ion Source Test Stand (ISTS), it was recognized that a higher current power Supply would be needed and work resumed on the regulator circuitry. A 120-kV power Supply having low output capacitance and a planar triode have been used to Supply 40 mA, 120-Hz, 12 % duty-factor current for the ISTS beam. The triode’s cathode current is controlled by circuitry operating both at power-Supply Voltage Level and at ground Level via a fiber optic link. Voltage droop is approximately 600 V during the 1 ms beam pulse. We present the status of the regulator and its special challenges.