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Marian K Kazimierczuk - One of the best experts on this subject based on the ideXlab platform.
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Design of Class E Power Amplifier with New Structure and Flat Top Switch Voltage Waveform
IEEE Transactions on Power Electronics, 2018Co-Authors: Mohsen Hayati, Sobhan Roshani, Marian K Kazimierczuk, Saeed Roshani, Hiroo SekiyaAbstract:In this paper, a new topology of the class E power amplifier (PA) is proposed. The output circuit in the proposed PA is different from that in the conventional class E PA. The conventional output circuit of class E PA consists of shunt capacitor, resonant capacitor, resonant inductor, and shifting inductor. An additional shunt capacitance is added between the resonant capacitance and the shifting inductor to shape the reduced Switch Voltage. The peak Switch Voltage of the proposed class E PA is approximately 78% of that of the conventional one, which shows a reduction in peak Switch Voltage. The lower peak Switch Voltage reduces the breakdown Voltage of the active device. Also, the proposed structure can introduce a new family of Switching PAs with interesting specifications. Several values of Switch Voltage reduction and output power capability could be achieved by varying the circuit elements. Zero Voltage and zero derivative Switching conditions are achieved in the Switch Voltage of the designed circuit. The simulation of the proposed circuit is performed using PSpice software. For verification, the presented PA is fabricated and measured.
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a class e power amplifier design considering mosfet nonlinear drain to source and nonlinear gate to drain capacitances at any grading coefficient
IEEE Transactions on Power Electronics, 2016Co-Authors: Mohsen Hayati, Sobhan Roshani, Marian K Kazimierczuk, Hiroo SekiyaAbstract:This paper presents theory and analysis for class-E power amplifier considering MOSFET nonlinear gate-to-drain and nonlinear drain-to-source capacitances at any grading coefficient of the MOSFET body junction diode. The nonlinearity degree of a MOSFET parasitic capacitance is determined by the grading coefficient. When the grading coefficient is not considered in design procedure, the Switch Voltage waveform of the class-E power amplifier does not satisfy the Switching conditions, which results in a decrease of the power conversion efficiency. Therefore, the grading coefficient is an important parameter to satisfy the class-E zero-Voltage Switching (ZVS) and zero-derivative Switching (ZDS) conditions. The MOSFET gate-to-drain capacitance is highly nonlinear, and it is more nonlinear than drain-to-source capacitance for most MOSFETs. In some cases, the change in the gate-to-drain capacitance can be as large as 100 times. The results show that this nonlinearity affects the class-E power amplifier properties, such as Switch Voltage, power output capability, and maximum Switch Voltage. Therefore, it is necessary to consider the nonlinearity of the gate-to-drain capacitance, along with the drain-to-source capacitance. A design example at 4 MHz operating frequency is also given to describe the design procedure. The ZVS and ZDS conditions are achieved in the obtained Switch Voltage. The circuit simulation was performed using PSpice software. For verification of the presented theory, a class-E power amplifier is fabricated. The measured results are verified with simulation and theory results.
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steady state analysis and design of class d zvs inverter at any duty ratio
IEEE Transactions on Power Electronics, 2016Co-Authors: Hiroo Sekiya, Marian K Kazimierczuk, Tomoharu Nagashima, Tadashi SuetsuguAbstract:This paper presents steady-state analytical expressions of the class-D zero-Voltage Switching inverter at any duty ratio along with a design example. The obtained expressions include stead-state Voltage and current waveforms, output power capability, peak Switch Voltage, peak Switch current, output power, and power conversion efficiency as functions of the duty ratio. Additionally, Switching-timing allowance due to antiparallel diodes of Switching devices can be predicted from the analytical results. The analytical expressions are verified by showing quantitative agreements with PSpice simulations and circuit experiments.
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analysis design and implementation of the class e zvs power amplifier with mosfet nonlinear drain to source parasitic capacitance at any grading coefficient
IEEE Transactions on Power Electronics, 2014Co-Authors: Mohsen Hayati, Marian K Kazimierczuk, Ali Lotfi, Hiroo SekiyaAbstract:In this paper, analytical expressions for waveforms and design relationships are derived for the class-E power amplifier with the MOSFET nonlinear drain-to-source parasitic capacitance under the subnominal operation, i.e., only zero-Voltage Switching (ZVS) condition, for any grading coefficient m of the MOSFET body junction diode and 50% duty ratio. Only the MOSFET nonlinear drain-to-source parasitic capacitance is used for the analysis of the class-E ZVS power amplifier, and its nonlinearity is determined by the grading coefficient m. The Switch Voltage waveform does not satisfy the class-E ZVS Switching condition when only the linear shunt capacitance is considered. The grading coefficient m is used as an adjustment parameter that provides accurate design to satisfy the given output power and peak Switch Voltage simultaneously. Therefore, the grading coefficient m is the important parameter to satisfy the class-E ZVS condition and given design specifications, which is the most important result in this paper. Additionally, the output power capability and maximum operating frequency are affected by the grading coefficient m. The analytical expressions are obtained by considering the grading coefficient m as an adjustment parameter, which is validated by PSpice simulations and laboratory experiments. The measurement and PSpice simulation results agreed with the analytical expressions quantitatively, which denotes the usefulness and effectiveness of our obtained analytical expressions.
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analysis and design of class e power amplifier with mosfet parasitic linear and nonlinear capacitances at any duty ratio
IEEE Transactions on Power Electronics, 2013Co-Authors: Mohsen Hayati, Marian K Kazimierczuk, Ali Lotfi, Hiroo SekiyaAbstract:This paper presents analytical expressions for the class-E power amplifier with MOSFET linear gate-to-drain and nonlinear drain-to-source parasitic capacitances at any duty ratio. The maximum operating frequency, output power capability, and element values as functions of the duty ratio are obtained. The element values are directly dependent upon the selection of duty ratio and require a careful duty ratio selection to minimize component power losses and to maximize the total efficiency. Two design examples at 25 and 9 W output power at 4-MHz operating frequency along with the PSpice-simulation and experimental waveforms are presented. It is shown from the derived expressions that the slope of the Voltage across the MOSFET gate-to-drain parasitic capacitance during the Switch-off state as a function of the duty ratio affects the Switch-Voltage waveform. Therefore, it is possible to achieve the required peak Switch Voltage and the class-E ZVS/ZVDS conditions simultaneously by adjusting the duty ratio. The theoretical results and PSpice simulations agreed with experimental results quantitatively, which shows the validity of the presented analysis.
Tadashi Suetsugu - One of the best experts on this subject based on the ideXlab platform.
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design of load independent class e inverter with mosfet parasitic capacitances
Midwest Symposium on Circuits and Systems, 2019Co-Authors: Weisen Luo, Xiuqin Wei, Hiroo Sekiya, Tadashi SuetsuguAbstract:This paper presents a numerical design method of the load-independent class-E inverter with MOSFET gate-to-drain and drain-to-source parasitic capacitances. A design example is shown along with its LTspice simulation and laboratory experiment. There are no changes in the output-Voltage waveforms and all the Switch-Voltage waveforms satisfy the zero-Voltage-Switching (ZVS) condition even the load-resistance value varies from the desired one. Additionally, the results obtained from the LTspice simulation and laboratory experiment show quantitative agreement with the numerical predictions, which shows the effectiveness of the proposed design method of the load-independent class-E inverter with MOSFET parasitic capacitances given in this paper.
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A control method of class E 2 DC-DC converter with adjustable peak Switch Voltage under input Voltage fluctuation
2017 IEEE 6th International Conference on Renewable Energy Research and Applications (ICRERA), 2017Co-Authors: Katsutoshi Hirayama, Tadashi Suetsugu, Fujio KurokawaAbstract:This paper presents a control method of class E2 dc-dc converter with adjustable the peak Switch Voltage under input Voltage fluctuation Class E2 dc-dc converter, which is one of the converter suitable for high operating frequency is studied. Class E2 dc-dc converter composed of a Class E amplifier and Class E rectifier. The amplifier side and rectifier side of class E2 dc-dc converter can achieve ZVS and ZDS. However, this converter can't cope with Voltage fluctuation of renewable energy. The proposed circuit uses a Voltage divider circuit on the amplifier side of the E2 class dc-dc converter. The peak Switch Voltage can be divided by the Voltage dividing circuit. Furthermore, by varying the number of transistors that are connected in series, the value of the shunt capacitance can be approximately changed. The peak Switch Voltage can be reduced, and by using the synchronous Switch, the output Voltage can also be kept constant when the input Voltage fluctuation.
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steady state analysis and design of class d zvs inverter at any duty ratio
IEEE Transactions on Power Electronics, 2016Co-Authors: Hiroo Sekiya, Marian K Kazimierczuk, Tomoharu Nagashima, Tadashi SuetsuguAbstract:This paper presents steady-state analytical expressions of the class-D zero-Voltage Switching inverter at any duty ratio along with a design example. The obtained expressions include stead-state Voltage and current waveforms, output power capability, peak Switch Voltage, peak Switch current, output power, and power conversion efficiency as functions of the duty ratio. Additionally, Switching-timing allowance due to antiparallel diodes of Switching devices can be predicted from the analytical results. The analytical expressions are verified by showing quantitative agreements with PSpice simulations and circuit experiments.
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Active Voltage clamping of class E amplifier
8th International Conference on Power Electronics - ECCE Asia, 2011Co-Authors: Tadashi SuetsuguAbstract:In this paper, a lossless Voltage clamp method with an auxiliary Switch is proposed as a remedy for the high peak Switch Voltage of the class E amplifier. In the proposed method, the auxiliary Switch is operated with synchronized drive circuit. Output power can be regulated by adjusting phase of auxiliary Switch.
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steady state behavior of class e amplifier outside designed conditions
International Symposium on Circuits and Systems, 2005Co-Authors: Tadashi Suetsugu, Marian K KazimierczukAbstract:Explicit expressions for steady-state behavior of the class E amplifier are derived. These equations are useful to predict the behavior of the class E amplifier outside the designed conditions. It is shown how the Switch Voltage and current waveforms change when duty cycle, frequency, or load resistance deviates from the designed values corresponding to zero-Voltage Switching/zero-derivative Switching conditions. The theory was compared with PSpice simulation.
Chenfeng Chuang - One of the best experts on this subject based on the ideXlab platform.
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a novel transformer less interleaved four phase step down dc converter with low Switch Voltage stress and automatic uniform current sharing characteristics
IEEE Transactions on Power Electronics, 2016Co-Authors: Chenfeng Chuang, Chingtsai Pan, Haochien ChengAbstract:In this paper, we propose a novel transformer-less direct current (dc) converter that features low Switch Voltage stress and automatic uniform current sharing. An interleaved four-phase Voltage divider operating from a 400 V dc bus is used to achieve a high step-down conversion ratio with a moderate duty ratio. Based on the capacitive Voltage division, the proposed converter achieves two major objectives, i.e., increased Voltage conversion ratio, due to energy storage in the blocking capacitors, and reduced Voltage stress of active Switches and diodes. As a result, the proposed converter permits the use of lower Voltage rating MOSFETs to reduce both Switching and conduction losses, thereby improving the overall efficiency. In addition, due to the charge balance of the capacitors, the proposed converter enables automatic uniform current sharing of the interleaved phases without adding extra circuitry or complex control methods. The operation principles and performance analyses of the proposed converter are presented, and its effectiveness is verified by a 500 W output power prototype circuit that converts 400 V input Voltage into 24 V output Voltage.
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a novel transformer less adaptable Voltage quadrupler dc converter with low Switch Voltage stress
IEEE Transactions on Power Electronics, 2014Co-Authors: Chenfeng ChuangAbstract:In this paper, a novel transformer-less adjustable Voltage quadrupler dc-dc converter with high-Voltage transfer gain and reduced semiconductor Voltage stress is proposed. The proposed topology utilizes input-parallel output-series configuration for providing a much higher Voltage gain without adopting an extreme large duty cycle. The proposed converter cannot only achieve high step-up Voltage gain with reduced component count but also reduce the Voltage stress of both active Switches and diodes. This will allow one to choose lower Voltage rating MOSFETs and diodes to reduce both Switching and conduction losses. In addition, due to the charge balance of the blocking capacitor, the converter features automatic uniform current sharing characteristic of the two interleaved phases for Voltage boosting mode without adding extra circuitry or complex control methods. The operation principle and steady analysis as well as a comparison with other recent existing high step-up topologies are presented. Finally, some simulation and experimental results are also presented to demonstrate the effectiveness of the proposed converter.
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a novel transformer less adaptable Voltage quadrupler dc converter with low Switch Voltage stress
IEEE Transactions on Power Electronics, 2014Co-Authors: Chingtsai Pan, Chenfeng Chuang, Chiachi ChuAbstract:In this paper, a novel transformer-less adjustable Voltage quadrupler dc-dc converter with high-Voltage transfer gain and reduced semiconductor Voltage stress is proposed. The proposed topology utilizes input-parallel output-series configuration for providing a much higher Voltage gain without adopting an extreme large duty cycle. The proposed converter cannot only achieve high step-up Voltage gain with reduced component count but also reduce the Voltage stress of both active Switches and diodes. This will allow one to choose lower Voltage rating MOSFETs and diodes to reduce both Switching and conduction losses. In addition, due to the charge balance of the blocking capacitor, the converter features automatic uniform current sharing characteristic of the two interleaved phases for Voltage boosting mode without adding extra circuitry or complex control methods. The operation principle and steady analysis as well as a comparison with other recent existing high step-up topologies are presented. Finally, some simulation and experimental results are also presented to demonstrate the effectiveness of the proposed converter.
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a novel transformerless interleaved high step down conversion ratio dc dc converter with low Switch Voltage stress
IEEE Transactions on Industrial Electronics, 2014Co-Authors: Chingtsai Pan, Chenfeng Chuang, Chiachi ChuAbstract:In this paper, a novel transformerless interleaved high step-down conversion ratio dc-dc converter with low Switch Voltage stress is proposed. In the proposed converter, two input capacitors are series-charged by the input Voltage and parallel-discharged by a new two-phase interleaved buck converter for providing a much higher step-down conversion ratio without adopting an extreme short duty cycle. Based on the capacitive Voltage division, the main objectives of the new Voltage-divider circuit in the converter are for both storing energy in the blocking capacitors for increasing the step-down conversion ratio and reducing Voltage stresses of active Switches. As a result, the proposed converter topology possesses the low Switch Voltage stress characteristic. This will allow one to choose lower Voltage rating MOSFETs to reduce both Switching and conduction losses, and the overall efficiency is consequently improved. Moreover, due to the charge balance of the blocking capacitor, the converter features automatic uniform current sharing characteristic of the interleaved phases without adding extra circuitry or complex control methods. The operation principles and relevant analysis of the proposed converter are presented in this paper. Finally, a 400-V input Voltage, 25-V output Voltage, and 400-W output power prototype circuit is implemented in the laboratory to verify the performance.
Chingtsai Pan - One of the best experts on this subject based on the ideXlab platform.
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a novel transformer less interleaved four phase step down dc converter with low Switch Voltage stress and automatic uniform current sharing characteristics
IEEE Transactions on Power Electronics, 2016Co-Authors: Chenfeng Chuang, Chingtsai Pan, Haochien ChengAbstract:In this paper, we propose a novel transformer-less direct current (dc) converter that features low Switch Voltage stress and automatic uniform current sharing. An interleaved four-phase Voltage divider operating from a 400 V dc bus is used to achieve a high step-down conversion ratio with a moderate duty ratio. Based on the capacitive Voltage division, the proposed converter achieves two major objectives, i.e., increased Voltage conversion ratio, due to energy storage in the blocking capacitors, and reduced Voltage stress of active Switches and diodes. As a result, the proposed converter permits the use of lower Voltage rating MOSFETs to reduce both Switching and conduction losses, thereby improving the overall efficiency. In addition, due to the charge balance of the capacitors, the proposed converter enables automatic uniform current sharing of the interleaved phases without adding extra circuitry or complex control methods. The operation principles and performance analyses of the proposed converter are presented, and its effectiveness is verified by a 500 W output power prototype circuit that converts 400 V input Voltage into 24 V output Voltage.
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a novel transformer less adaptable Voltage quadrupler dc converter with low Switch Voltage stress
IEEE Transactions on Power Electronics, 2014Co-Authors: Chingtsai Pan, Chenfeng Chuang, Chiachi ChuAbstract:In this paper, a novel transformer-less adjustable Voltage quadrupler dc-dc converter with high-Voltage transfer gain and reduced semiconductor Voltage stress is proposed. The proposed topology utilizes input-parallel output-series configuration for providing a much higher Voltage gain without adopting an extreme large duty cycle. The proposed converter cannot only achieve high step-up Voltage gain with reduced component count but also reduce the Voltage stress of both active Switches and diodes. This will allow one to choose lower Voltage rating MOSFETs and diodes to reduce both Switching and conduction losses. In addition, due to the charge balance of the blocking capacitor, the converter features automatic uniform current sharing characteristic of the two interleaved phases for Voltage boosting mode without adding extra circuitry or complex control methods. The operation principle and steady analysis as well as a comparison with other recent existing high step-up topologies are presented. Finally, some simulation and experimental results are also presented to demonstrate the effectiveness of the proposed converter.
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a novel transformerless interleaved high step down conversion ratio dc dc converter with low Switch Voltage stress
IEEE Transactions on Industrial Electronics, 2014Co-Authors: Chingtsai Pan, Chenfeng Chuang, Chiachi ChuAbstract:In this paper, a novel transformerless interleaved high step-down conversion ratio dc-dc converter with low Switch Voltage stress is proposed. In the proposed converter, two input capacitors are series-charged by the input Voltage and parallel-discharged by a new two-phase interleaved buck converter for providing a much higher step-down conversion ratio without adopting an extreme short duty cycle. Based on the capacitive Voltage division, the main objectives of the new Voltage-divider circuit in the converter are for both storing energy in the blocking capacitors for increasing the step-down conversion ratio and reducing Voltage stresses of active Switches. As a result, the proposed converter topology possesses the low Switch Voltage stress characteristic. This will allow one to choose lower Voltage rating MOSFETs to reduce both Switching and conduction losses, and the overall efficiency is consequently improved. Moreover, due to the charge balance of the blocking capacitor, the converter features automatic uniform current sharing characteristic of the interleaved phases without adding extra circuitry or complex control methods. The operation principles and relevant analysis of the proposed converter are presented in this paper. Finally, a 400-V input Voltage, 25-V output Voltage, and 400-W output power prototype circuit is implemented in the laboratory to verify the performance.
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a high efficiency high step up converter with low Switch Voltage stress for fuel cell system applications
IEEE Transactions on Industrial Electronics, 2010Co-Authors: Chingtsai Pan, Chingming LaiAbstract:In this paper, a novel high step-up converter is proposed for fuel-cell system applications. As an illustration, a two-phase version configuration is given for demonstration. First, an interleaved structure is adapted for reducing input and output ripples. Then, a C?uk-type converter is integrated to the first phase to achieve a much higher Voltage conversion ratio and avoid operating at extreme duty ratio. In addition, additional capacitors are added as Voltage dividers for the two phases for reducing the Voltage stress of active Switches and diodes, which enables one to adopt lower Voltage rating devices to further reduce both Switching and conduction losses. Furthermore, the corresponding model is also derived, and analysis of the steady-state characteristic is made to show the merits of the proposed converter. Finally, a 200-W rating prototype system is also constructed to verify the effectiveness of the proposed converter. It is seen that an efficiency of 93.3% can be achieved when the output power is 150-W and the output Voltage is 200-V with 0.56 duty ratio.
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Integrated Single-Phase Inverter with an Auxiliary Step-Up Circuit for Low-Voltage Alternative Energy Source Applications
2010 Asia-Pacific Power and Energy Engineering Conference, 2010Co-Authors: Chingtsai Pan, Ming-chieh Cheng, Chingming Lai, Ching-min ChungAbstract:[[abstract]]This paper presents a integrated single-phase inverter with both high step-up ratio and buck-boost capabilities for low Voltage alternative energy sources applications. An auxiliary step-up circuit is integrated to the isolated Cuk-derived VSI to achieve a much higher Voltage conversion ratio while avoiding the use of extreme duty ratios of both dc-side Switches and inverter-side Switches. The proposed inverter can naturally perform capacitive charging in parallel and discharging in series to give a higher Voltage level without increasing dc-side Switch Voltage stress and sacrificing the buck-boost characteristics of the ac output Voltage. Steady-state characteristics, performance analyses and comprehensive experimental results are made to show the merits of the proposed inverter.[[fileno]]2030146030204[[department]]電機工程學
Hiroo Sekiya - One of the best experts on this subject based on the ideXlab platform.
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design of load independent class e inverter with mosfet parasitic capacitances
Midwest Symposium on Circuits and Systems, 2019Co-Authors: Weisen Luo, Xiuqin Wei, Hiroo Sekiya, Tadashi SuetsuguAbstract:This paper presents a numerical design method of the load-independent class-E inverter with MOSFET gate-to-drain and drain-to-source parasitic capacitances. A design example is shown along with its LTspice simulation and laboratory experiment. There are no changes in the output-Voltage waveforms and all the Switch-Voltage waveforms satisfy the zero-Voltage-Switching (ZVS) condition even the load-resistance value varies from the desired one. Additionally, the results obtained from the LTspice simulation and laboratory experiment show quantitative agreement with the numerical predictions, which shows the effectiveness of the proposed design method of the load-independent class-E inverter with MOSFET parasitic capacitances given in this paper.
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Design of Class E Power Amplifier with New Structure and Flat Top Switch Voltage Waveform
IEEE Transactions on Power Electronics, 2018Co-Authors: Mohsen Hayati, Sobhan Roshani, Marian K Kazimierczuk, Saeed Roshani, Hiroo SekiyaAbstract:In this paper, a new topology of the class E power amplifier (PA) is proposed. The output circuit in the proposed PA is different from that in the conventional class E PA. The conventional output circuit of class E PA consists of shunt capacitor, resonant capacitor, resonant inductor, and shifting inductor. An additional shunt capacitance is added between the resonant capacitance and the shifting inductor to shape the reduced Switch Voltage. The peak Switch Voltage of the proposed class E PA is approximately 78% of that of the conventional one, which shows a reduction in peak Switch Voltage. The lower peak Switch Voltage reduces the breakdown Voltage of the active device. Also, the proposed structure can introduce a new family of Switching PAs with interesting specifications. Several values of Switch Voltage reduction and output power capability could be achieved by varying the circuit elements. Zero Voltage and zero derivative Switching conditions are achieved in the Switch Voltage of the designed circuit. The simulation of the proposed circuit is performed using PSpice software. For verification, the presented PA is fabricated and measured.
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A Novel High-Speed SiC MOSFET Driver with a Low Switch-Voltage Stress
2018 International Power Electronics Conference (IPEC-Niigata 2018 -ECCE Asia), 2018Co-Authors: Xiuqin Wei, Yuchong Sun, Hiroo SekiyaAbstract:A novel high-speed SiC MOSFET driver with a low Switch-Voltage stress is presented in this paper. In the proposed driver, a harmonic component is injected to the conventional class-E inverter. Consequently, the class-E driver proposed in this paper not only maintains the strong points of the conventional class-E inverter, such as simple topology and high-frequency high-efficiency operation, but also has its own advantage of low Switch-Voltage stress. The proposed class-E driver is designed in this paper. Additionally, the PSpice-simulation and laboratory experiment are carried out. It can be seen from the PSpice-simulation and experimental results that all the Switch-Voltage waveforms satisfy the zero-Voltage Switching (ZVS) and zero-derivative Switching (ZDS) conditions. Therefore, the proposed class-E driver is available in the high-frequency and high-efficiency applications. Moreover, a quite lower Switch-Voltage stress is obtained in the proposed class-E driver. The simulated and experimental results agreed with the theoretical one well. These results mentioned before demonstrated the proposed driver’s validity.
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a class e power amplifier design considering mosfet nonlinear drain to source and nonlinear gate to drain capacitances at any grading coefficient
IEEE Transactions on Power Electronics, 2016Co-Authors: Mohsen Hayati, Sobhan Roshani, Marian K Kazimierczuk, Hiroo SekiyaAbstract:This paper presents theory and analysis for class-E power amplifier considering MOSFET nonlinear gate-to-drain and nonlinear drain-to-source capacitances at any grading coefficient of the MOSFET body junction diode. The nonlinearity degree of a MOSFET parasitic capacitance is determined by the grading coefficient. When the grading coefficient is not considered in design procedure, the Switch Voltage waveform of the class-E power amplifier does not satisfy the Switching conditions, which results in a decrease of the power conversion efficiency. Therefore, the grading coefficient is an important parameter to satisfy the class-E zero-Voltage Switching (ZVS) and zero-derivative Switching (ZDS) conditions. The MOSFET gate-to-drain capacitance is highly nonlinear, and it is more nonlinear than drain-to-source capacitance for most MOSFETs. In some cases, the change in the gate-to-drain capacitance can be as large as 100 times. The results show that this nonlinearity affects the class-E power amplifier properties, such as Switch Voltage, power output capability, and maximum Switch Voltage. Therefore, it is necessary to consider the nonlinearity of the gate-to-drain capacitance, along with the drain-to-source capacitance. A design example at 4 MHz operating frequency is also given to describe the design procedure. The ZVS and ZDS conditions are achieved in the obtained Switch Voltage. The circuit simulation was performed using PSpice software. For verification of the presented theory, a class-E power amplifier is fabricated. The measured results are verified with simulation and theory results.
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steady state analysis and design of class d zvs inverter at any duty ratio
IEEE Transactions on Power Electronics, 2016Co-Authors: Hiroo Sekiya, Marian K Kazimierczuk, Tomoharu Nagashima, Tadashi SuetsuguAbstract:This paper presents steady-state analytical expressions of the class-D zero-Voltage Switching inverter at any duty ratio along with a design example. The obtained expressions include stead-state Voltage and current waveforms, output power capability, peak Switch Voltage, peak Switch current, output power, and power conversion efficiency as functions of the duty ratio. Additionally, Switching-timing allowance due to antiparallel diodes of Switching devices can be predicted from the analytical results. The analytical expressions are verified by showing quantitative agreements with PSpice simulations and circuit experiments.
