The Experts below are selected from a list of 49527 Experts worldwide ranked by ideXlab platform
Jihwan P. Choi - One of the best experts on this subject based on the ideXlab platform.
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Predicting System Failure Rates of SRAM-based FPGA on-board processors in space radiation environments
Reliability Engineering & System Safety, 2019Co-Authors: Seunghwa Jung, Jihwan P. ChoiAbstract:Abstract Static random-access memory-based field-programmable gate arrays are increasingly being used for on-board processors in space missions. However, they are very susceptible to single event upsets that can geneRate on-board processor System malfunction or System Failures in space radiation environments. This paper presents an on-board processor System adopting Triple Modular Redundancy with the concept of mitigation windows and external scrubber, and then suggests a mathematical model that predicts the on-board processor System Failure Rate by only using the information of System configuration resources. Our mathematical derivation can estimate on-board processor System reliability as a function of the single event upset Rate, the number of mitigation windows, and on-board processor shield thickness. In addition, a guideline of the on-board processor System design is provided for achieving good single event upset mitigation capability and System reliability.
Zainalabedin Navabi - One of the best experts on this subject based on the ideXlab platform.
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Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC
2007Co-Authors: Mohammad Hosseinabady, Mohammad Neishaburi, Zainalabedin Navabi, Alfredo Benso, Paolo Prinetto, Stefano Di Carlo, Giorgio Di NataleAbstract:This paper proposes an analytical method to assess the soft-error Rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML (Unified Modeling Language) model of the SoC and the raw soft-error Rate of different parts of the platform as its inputs. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. The Dynamic behavior of each core is used to determine the propagation probability of each variable disturbance to the core outputs. Furthermore, the SER and the execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each Failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC.
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Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC
2007Co-Authors: Mohammad Hosseinabady, Mohammad Neishaburi, Zainalabedin Navabi, Alfredo Benso, Paolo Prinetto, Stefano Di Carlo, Giorgio Di NataleAbstract:This paper proposes an analytical method to assess the soft-error Rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML (Unified Modeling Language) model of the SoC and the raw soft-error Rate of different parts of the platform as its inputs. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. The Dynamic behavior of each core is used to determine the propagation probability of each variable disturbance to the core outputs. Furthermore, the SER and the execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each Failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC.
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a uml based System level Failure Rate assessment technique for soc designs
VLSI Test Symposium, 2007Co-Authors: Mohammad Hosseinabady, Mohammad Neishaburi, Pejman Lotfikamran, Zainalabedin NavabiAbstract:This paper proposes an analytical method to assess soft-error Rate (SER) in the early stages of a System-on-chip (SoC) platform-based design methodology. The proposed method uses an executable UML model of the SoC for its input. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. SER and execution time of each core in the SoC and a Failure modes and effects analysis (FMEA) that determines the severity of each Failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC
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IOLTS - Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC
13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007Co-Authors: Mohammad Hosseinabady, Mohammad Neishaburi, Zainalabedin Navabi, Alfredo Benso, Paolo Prinetto, Stefano Di Carlo, Giorgio Di NataleAbstract:This paper proposes an analytical method to assess the soft-error Rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML (Unified Modeling Language) model of the SoC and the raw soft- error Rate of different parts of the platform as its inputs. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. The Dynamic behavior of each core is used to determine the propagation probability of each variable disturbance to the core outputs. Furthermore, the SER and the execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each Failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC.
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VTS - A UML Based System Level Failure Rate Assessment Technique for SoC Designs
25th IEEE VLSI Test Symmposium (VTS'07), 2007Co-Authors: Mohammad Hosseinabady, Mohammad Neishaburi, Pejman Lotfi-kamran, Zainalabedin NavabiAbstract:This paper proposes an analytical method to assess soft-error Rate (SER) in the early stages of a System-on-chip (SoC) platform-based design methodology. The proposed method uses an executable UML model of the SoC for its input. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. SER and execution time of each core in the SoC and a Failure modes and effects analysis (FMEA) that determines the severity of each Failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC
Mohammad Hosseinabady - One of the best experts on this subject based on the ideXlab platform.
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Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC
2007Co-Authors: Mohammad Hosseinabady, Mohammad Neishaburi, Zainalabedin Navabi, Alfredo Benso, Paolo Prinetto, Stefano Di Carlo, Giorgio Di NataleAbstract:This paper proposes an analytical method to assess the soft-error Rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML (Unified Modeling Language) model of the SoC and the raw soft-error Rate of different parts of the platform as its inputs. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. The Dynamic behavior of each core is used to determine the propagation probability of each variable disturbance to the core outputs. Furthermore, the SER and the execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each Failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC.
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Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC
2007Co-Authors: Mohammad Hosseinabady, Mohammad Neishaburi, Zainalabedin Navabi, Alfredo Benso, Paolo Prinetto, Stefano Di Carlo, Giorgio Di NataleAbstract:This paper proposes an analytical method to assess the soft-error Rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML (Unified Modeling Language) model of the SoC and the raw soft-error Rate of different parts of the platform as its inputs. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. The Dynamic behavior of each core is used to determine the propagation probability of each variable disturbance to the core outputs. Furthermore, the SER and the execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each Failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC.
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a uml based System level Failure Rate assessment technique for soc designs
VLSI Test Symposium, 2007Co-Authors: Mohammad Hosseinabady, Mohammad Neishaburi, Pejman Lotfikamran, Zainalabedin NavabiAbstract:This paper proposes an analytical method to assess soft-error Rate (SER) in the early stages of a System-on-chip (SoC) platform-based design methodology. The proposed method uses an executable UML model of the SoC for its input. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. SER and execution time of each core in the SoC and a Failure modes and effects analysis (FMEA) that determines the severity of each Failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC
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IOLTS - Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC
13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007Co-Authors: Mohammad Hosseinabady, Mohammad Neishaburi, Zainalabedin Navabi, Alfredo Benso, Paolo Prinetto, Stefano Di Carlo, Giorgio Di NataleAbstract:This paper proposes an analytical method to assess the soft-error Rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML (Unified Modeling Language) model of the SoC and the raw soft- error Rate of different parts of the platform as its inputs. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. The Dynamic behavior of each core is used to determine the propagation probability of each variable disturbance to the core outputs. Furthermore, the SER and the execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each Failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC.
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VTS - A UML Based System Level Failure Rate Assessment Technique for SoC Designs
25th IEEE VLSI Test Symmposium (VTS'07), 2007Co-Authors: Mohammad Hosseinabady, Mohammad Neishaburi, Pejman Lotfi-kamran, Zainalabedin NavabiAbstract:This paper proposes an analytical method to assess soft-error Rate (SER) in the early stages of a System-on-chip (SoC) platform-based design methodology. The proposed method uses an executable UML model of the SoC for its input. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. SER and execution time of each core in the SoC and a Failure modes and effects analysis (FMEA) that determines the severity of each Failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC
Hamid Reza Zarandi - One of the best experts on this subject based on the ideXlab platform.
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An adaptive method to toleRate soft errors in SRAM-based FPGAs
Scientia Iranica, 2011Co-Authors: Somayeh Bahramnejad, Hamid Reza ZarandiAbstract:Abstract In this paper, we present an adaptive method that is a combination of SEU-avoidance in CAD flow and adaptive redundancy to toleRate soft error effects in SRAM-based FPGAs. This method is based on the modification of T-VPack and VPR tools. Three different steps of these tools are modified for SEU-awareness: (1) clustering, (2) placement and (3) routing. Then we use the unused resources as redundancy. We have investigated the effect of this method on several MCNC benchmarks. This investigation has been performed using three experiments: (1) SEU-awareness in clustering with redundancy, (2) SEU-awareness in clustering and placement with redundancy and (3) SEU-awareness in clustering, placement and routing with redundancy. With a confidence level of 95%, the results show that, using each of these three experiments, the System Failure Rate of ten MCNC circuits has been decreased between 4.52% and 10.42%, between 10.25% and 21.63%, and between 10.48% and 24.39%, respectively.
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Mitigation of soft errors in SRAM-based FPGAs using CAD tools
Computers & Electrical Engineering, 2011Co-Authors: Somayeh Bahramnejad, Hamid Reza ZarandiAbstract:This paper presents three methods to reduce the System Failures resulted from soft errors: (1) an adaptive redundancy-based method that utilizes unused resources to toleRate the effects of soft errors in SRAM-based FPGAs; (2) an SEU-aware method in CAD flow of SRAM-based FPGAs to mitigate the effects of soft errors which is based on T-VPack and VPR tools and functions without any redundancy; and finally, (3) combination of these two methods to realize whether these SEU reduction methods are cumulative or not when they are applied in sequence. The effects of these methods have been investigated on several MCNC benchmarks. The results show that the System Failure Rate of circuits implemented on FPGAs decreases about 3.59% using the first method, 4.60%, 10.09%, and 12.45% in three cases of the second method, and 7.47%, 15.94%, and 17.43% in three cases of the third method. These results show that the effect of combining the first and the second methods is cumulative.
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ARES - An Adaptive Redundancy Oriented Method to ToleRate Soft Errors in SRAM-Based FPGAs Using Unused Resources
2010 International Conference on Availability Reliability and Security, 2010Co-Authors: Somayeh Bahramnejad, Hamid Reza ZarandiAbstract:In this paper, we present an adaptive SEU-tolerance method based on redundancy for implementing circuits in SRAM-based FPGAs to toleRate soft error effects. This method uses unused resources for partial redundancy based on a property of nets called System Failure Rate (SFR). SFR of a given net is the probability of System Failure when the net is faulty. The redundancy is performed based on available resources, adaptively, so that System Failure Rate of circuit implemented in SRAM-based FPGAs decreases. We have investigated the effect of partial redundancy on several MCNC benchmarks. The results show that if maximum tolerable overall overhead is 20%, SFR increases up to 13%.
Yiyu Shi - One of the best experts on this subject based on the ideXlab platform.
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On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016Co-Authors: Tao Wang, Chun Zhang, Jinjun Xiong, Pei-wen Luo, Liang-chia Cheng, Yiyu ShiAbstract:Runtime noise management Systems typically rely on on-chip noise sensors to accuRately capture voltage emergencies. As such, the threshold voltage for noise sensors to report emergencies serves as a critical tuning knob between the System Failure Rate and false alarms. Unfortunately, the problem of optimal threshold voltage computation remains open in literature despite its importance. The problem is further complicated by process variations, which introduce significant variations in load currents and thus in noise across different chips. A uniform noise margin may not work optimally for all the chips. In this paper, we first formulate the problem of minimizing the System alarm Rate subject to a given System Failure Rate constraint. We then put forward a uniform scheme to find an optimal solution for all chips. Compared to a seemingly more intuitive approach which is too conservative, experimental results over a set of industrial designs show an average of 20.6% reduction in System alarm Rate under the same System Failure Rate constraint. We further show that with the help of ${I} _{\mathrm {ddq}}$ measurements during testing which reveal process variation information, it is possible and efficient to compute a per-chip optimal threshold voltage threshold. It further reduces the alarm Rate by 12.3% on average compared with uniform threshold approach. To the best of the authors knowledge, this is the first in-depth study on optimal threshold voltage computation for noise sensors. We hope that it shall point out new directions for Systematic studies of on-chip noise sensor utilization.
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ICCAD - Variation aware optimal threshold voltage computation for on-chip noise sensors
2014 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2014Co-Authors: Tao Wang, Chun Zhang, Jinjun Xiong, Pei-wen Luo, Liang-chia Cheng, Yiyu ShiAbstract:Runtime noise management Systems typically respond to on-chip noise sensors to accuRately capture voltage emergencies. As such, the threshold voltage for noise sensors to report emergencies serves as a critical tuning knob between the System Failure Rate and the runtime performance loss (RPL) due to false alarms. Unfortunately, the problem of optimal threshold voltage computation remains open in literature despite its importance. The problem is further complicated by process variations, which introduce significant variations in load currents and thus in noise across different chips. A uniform noise margin may not work optimally for all the chips. In this paper, we first formulate the problem of minimizing the System Failure Rate subject to a given RPL constraint. We then put forward a uniform scheme to find an optimal solution for all chips. Compared to a seemingly more intuitive approach which is too conservative, experimental results over a set of industrial designs show an average of 32.1% reduction in System Failure Rate under the same RPL constraint. We further show that with the help of I ddq measurements during testing which reveals process variation information, it is possible and efficient to compute a per-chip optimal threshold voltage. Such an approach further reduces the System Failure Rate by 25.0% on average compared with the uniform threshold approach, under the same RPL constraint. To the best of the authors knowledge, this is the first in-depth study on optimal threshold voltage computation for noise sensors. We hope that it shall point out new directions for Systematic studies of on-chip noise sensor utilization.
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On the Deployment of On-Chip Noise Sensors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014Co-Authors: Tao Wang, Chun Zhang, Jinjun Xiong, Yiyu ShiAbstract:Runtime noise management Systems can enforce power integrity without significantly increasing design margins. These Systems typically respond to on-chip noise sensors to accuRately capture voltage emergencies. Unfortunately, it remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection, or how to best set the threshold voltage for these sensors. In this paper, we formally define the problem of noise sensor placement along with a novel sensing quality metric to be maximized. We then put forward an efficient algorithm to solve it, which is proven to attain the best result in the class of polynomial complexity approximations. We further solve the problem to minimize the System Failure Rate subject to a given runtime performance loss (RPL) constraint. Experimental results on a set of industrial power grid designs show that, compared to a simple average-noise based heuristic and two state-of-the-art temperature sensor placement algorithms aimed at recovering the full map or capturing the hot spots at all times, the proposed method on average can reduce the miss Rate of voltage emergency detections by 7.4x, 15x, and 6.2x, respectively. The trade-off between the System Failure Rate and the RPL is also presented. To the best of the authors' knowledge, this is the very first in-depth work on noise sensor deployment.
