The Experts below are selected from a list of 61350 Experts worldwide ranked by ideXlab platform
Hoi-jun Yoo - One of the best experts on this subject based on the ideXlab platform.
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ISCAS - A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for Dynamic Voltage and Frequency Scaling
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Jeabin Lee, Seongjun Song, Byeong-gyu Nam, Namjun Cho, Hoi-jun YooAbstract:A power management unit (PMU) architecture is proposed for the domain-specific low power management with dynamic voltage and frequency scaling. The PMU continuously co-locks and dynamically varies the supply voltage and the clock frequency from 89 MHz to 200 MHz and from 1.0 V to 1.8 V, respectively, in less than 40mus. A 32bit RISC processor is used as power management Target Device. The PMU, 0.36mm2 with 0.18-mum CMOS process, consumes 5mW, and shows -100dBm/Hz phase noise of clock and 160mV load regulation of supply voltage with 100mA load current from the load, RISC processor.
Amir Moradi - One of the best experts on this subject based on the ideXlab platform.
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Template attacks on nano-scale CMOS Devices
Journal of Cryptographic Engineering, 2020Co-Authors: Bastian Richter, Amir MoradiAbstract:Profiled attacks are widely considered to be the most powerful form of side-channel analysis attacks. A common form is known as Gaussian template attacks which fit a Gaussian distribution to better model the behavior of the Target Device. Since profiled attacks build the model based on a Device identical to the Target Device, manufacturing variances are an important factor for the success of such attacks. With shrinking the feature size, the influence of manufacturing variation on the power consumption of integrated circuits increases. It has been warned that this issue might render template attacks less effective. We evaluate this assumption on an ASIC design manufactured in 40 nm technology. We characterize the introduced variation and show that these can be easily mitigated. By performing attacks on multiple samples of the same ASIC, we show that template attacks on small technology sizes are still successful.
Michael Tunstall - One of the best experts on this subject based on the ideXlab platform.
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Online template attacks
Journal of Cryptographic Engineering, 2019Co-Authors: Lejla Batina, Łukasz Chmielewski, Louiza Papachristodoulou, Peter Schwabe, Michael TunstallAbstract:Template attacks are a special kind of side-channel attacks that work in two stages. In a first stage, the attacker builds up a database of template traces collected from a Device which is identical to the attacked Device, but under the attacker’s control. In the second stage, traces from the Target Device are compared to the template traces to recover the secret key. In the context of attacking elliptic curve scalar multiplication with template attacks, one can interleave template generation and template matching and reduce the amount of template traces. This paper enhances the power of this technique by defining and applying the concept of online template attacks , a general attack technique with minimal assumptions for an attacker, who has very very limited control over the template Device. We show that online template attacks need only one power consumption trace of a scalar multiplication on the Target Device; they are thus suitable not only against ECDSA and static elliptic curve Diffie–Hellman (ECDH), but also against elliptic curve scalar multiplication in ephemeral ECDH. In addition, online template attacks need only one template trace per scalar bit and they can be applied to a broad variety of scalar multiplication algorithms. To demonstrate the power of online template attacks, we recover scalar bits of a scalar multiplication using the double-and-add-always algorithm on a twisted Edwards curve running on a smartcard with an ATmega163 CPU.
Gilles Grimaud - One of the best experts on this subject based on the ideXlab platform.
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AhM of time deparment in ROM of a Java-OS
Lecture Notes in Computer Science, 2005Co-Authors: Kevin Marquet, Alexandre Courbot, Gilles GrimaudAbstract:This article shows how it is possible to place a great part of a Java system in read-only memory in order to fit with the requirements of tiny Devices. Java systems for such Devices are commonly deployed off-board, then embedded on the Target Device in a ready-to-run form. Our approach is to go as far as possible in this deployment, in order to maximize the amount of data placed in read-only memory. Doing so, we are also able to reduce the overall size of the system.
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ICESS - Ahead of time deployment in ROM of a Java-OS
Embedded Software and Systems, 2005Co-Authors: Kevin Marquet, Alexandre Courbot, Gilles GrimaudAbstract:This article shows how it is possible to place a great part of a Java system in read-only memory in order to fit with the requirements of tiny Devices. Java systems for such Devices are commonly deployed off-board, then embedded on the Target Device in a ready-to-run form. Our approach is to go as far as possible in this deployment, in order to maximize the amount of data placed in read-only memory. Doing so, we are also able to reduce the overall size of the system.
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Ahead of time deployment in ROM of a Java-OS
2005Co-Authors: Kevin Marquet, Alexandre Courbot, Gilles Grimaud, David Simplot-rylAbstract:This article shows how it is possible to place a great part of a Java system in read-only memory in order to fit with the requirements of tiny Devices. Java systems for such Devices are commonly deployed off-board, then embedded on the Target Device in a ready-to-run form. Our approach is reach an advanced state of deployment off-board, which allows us to maximize the amount of data placed in read-only memory. Doing so, we are also able to reduce the overall size of the system.
Rajesh Mehra - One of the best experts on this subject based on the ideXlab platform.
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Optimized Design of CIC Decimator using Embedded LUTs of FPGA for Wireless Communication Systems
2015Co-Authors: Rajesh Mehra, Swapna DeviAbstract:Abstract—In this paper an efficient multiplier less technique is presented to design a high speed CIC decimator for wireless applications like SDR and GSM. The implementation is based on efficient utilization of embedded LUTs of Target Device to enhance the speed of proposed design. It is an efficient method because the use of embedded LUTs not only increases the speed but also saves the resources on the Target Device. The fully pipelined CIC decimator is designed with Matlab, simulated with Modelsim, synthesized with Xilinx Synthesis Tool (XST), and implemented on Spartan-3E based XC3s500e-4fg320 Target Device. The proposed design can be operated at an estimated frequency of 206.2 MHz by consuming considerably less available resources of Target Device to provide cost effective solution for SDR applications. The power consumption of the proposed design is 0.08098W at 27.1°C junction temperature. Keywords—ASIC, CIC, FPGA, GSM, SD
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FPGA-Based Design of High-Speed CIC Decimator for Wireless Applications
2015Co-Authors: Rajesh Mehra, Rashmi AroraAbstract:Abstract — In this paper an efficient multiplier-less technique is presented to design and implement a high speed CIC decimator for wireless applications like SDR and GSM. The Cascaded Integrator Comb is a commonly used decimation filter which performs sample rate conversion (SRC) using only additions/subtractions. The implementation is based on efficient utilization of embedded LUTs of the Target Device to enhance the speed of proposed design. It is an efficient method used to design and implement CIC decimator because the use of embedded LUTs not only increases the speed but also saves the resources on the Target Device. The fully pipelined CIC decimator is designed with Matlab, simulated with Xilinx AccelDSP, synthesized with Xilinx Synthesis Tool (XST), and implemented on Virtex-II based XC2VP50-6 Target FPGA Device. The proposed design can operate at an estimated frequency of 276.6 MHz by consuming considerably less resources on Target Device to provide cost effective solution for SDR based wireless applications. Keywords- CIC; FPGA; FPGA; GSM; LUT; SDR. I
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FPGA Design of Optimized CIC Interpolator for DSP based Wireless Communication Systems
2010Co-Authors: Rajesh MehraAbstract:In this paper an efficient multiplier less technique is presented to design and implement a high speed CIC interpolator for wireless applications like SDR and GSM. The implementation is based on efficient utilization of embedded LUTs of the Target Device to enhance the speed of proposed design. It is an efficient method used to design and implement CIC interpolator because the use of embedded LUTs not only increases the speed but also saves the resources on the Target Device. The fully pipelined CIC interpolator has been designed with Matlab, simulated with Modelsim, synthesized with Xilinx Synthesis Tool (XST), and implemented on Spartan-3E based XC3s500e- 4fg320 Target Device. The proposed design can be operated at an estimated frequency of 166.5 MHz by consuming very less resources available on Target Device to provide cost effective solution for wireless communication systems. The power consumption of the proposed design has been 0.08098W at 27.1 degree C junction temperature.
