The Experts below are selected from a list of 87 Experts worldwide ranked by ideXlab platform
Z Navabi - One of the best experts on this subject based on the ideXlab platform.
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Test Instruction set tis for high level self Testing of cpu cores
Asian Test Symposium, 2004Co-Authors: Saeed Shamshiri, H Esmaeilzadeh, Z NavabiAbstract:TIS (Test Instruction set) is an Instruction level technique for CPU core self-Testing. This method is based on enhancing a CPU Instruction set with Test Instructions. TIS replaces the NOP Instruction that is available in most processors with Test Instructions so that online Testing can be done with no performance penalty. This method can be applied to both offline and online (concurrent) Testing of all types of processors (single-cycle, multi-cycle and pipelined). TIS is appropriate for pipelined architectures in which one or many NOP Instructions (or stalls) are inserted between Instructions that are data or control dependent. We have implemented this Test method on a pipelined CPU core and several Test programs for this pipelined CPU are used to illustrate the method. Also fault coverage results are presented to demonstrate the effectiveness of the TIS Test technique.
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Asian Test Symposium - Test Instruction set (TIS) for high level self-Testing of CPU cores
13th Asian Test Symposium, 2004Co-Authors: Saeed Shamshiri, H Esmaeilzadeh, Z NavabiAbstract:TIS (Test Instruction set) is an Instruction level technique for CPU core self-Testing. This method is based on enhancing a CPU Instruction set with Test Instructions. TIS replaces the NOP Instruction that is available in most processors with Test Instructions so that online Testing can be done with no performance penalty. This method can be applied to both offline and online (concurrent) Testing of all types of processors (single-cycle, multi-cycle and pipelined). TIS is appropriate for pipelined architectures in which one or many NOP Instructions (or stalls) are inserted between Instructions that are data or control dependent. We have implemented this Test method on a pipelined CPU core and several Test programs for this pipelined CPU are used to illustrate the method. Also fault coverage results are presented to demonstrate the effectiveness of the TIS Test technique.
Saeed Shamshiri - One of the best experts on this subject based on the ideXlab platform.
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Test Instruction set tis for high level self Testing of cpu cores
Asian Test Symposium, 2004Co-Authors: Saeed Shamshiri, H Esmaeilzadeh, Z NavabiAbstract:TIS (Test Instruction set) is an Instruction level technique for CPU core self-Testing. This method is based on enhancing a CPU Instruction set with Test Instructions. TIS replaces the NOP Instruction that is available in most processors with Test Instructions so that online Testing can be done with no performance penalty. This method can be applied to both offline and online (concurrent) Testing of all types of processors (single-cycle, multi-cycle and pipelined). TIS is appropriate for pipelined architectures in which one or many NOP Instructions (or stalls) are inserted between Instructions that are data or control dependent. We have implemented this Test method on a pipelined CPU core and several Test programs for this pipelined CPU are used to illustrate the method. Also fault coverage results are presented to demonstrate the effectiveness of the TIS Test technique.
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Asian Test Symposium - Test Instruction set (TIS) for high level self-Testing of CPU cores
13th Asian Test Symposium, 2004Co-Authors: Saeed Shamshiri, H Esmaeilzadeh, Z NavabiAbstract:TIS (Test Instruction set) is an Instruction level technique for CPU core self-Testing. This method is based on enhancing a CPU Instruction set with Test Instructions. TIS replaces the NOP Instruction that is available in most processors with Test Instructions so that online Testing can be done with no performance penalty. This method can be applied to both offline and online (concurrent) Testing of all types of processors (single-cycle, multi-cycle and pipelined). TIS is appropriate for pipelined architectures in which one or many NOP Instructions (or stalls) are inserted between Instructions that are data or control dependent. We have implemented this Test method on a pipelined CPU core and several Test programs for this pipelined CPU are used to illustrate the method. Also fault coverage results are presented to demonstrate the effectiveness of the TIS Test technique.
Behzad Nazari - One of the best experts on this subject based on the ideXlab platform.
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Teach-to-Test Instruction of Dynamic Assessment: A Critical Movement to Raise Grammar
Modern Journal of Language Teaching Methods, 2015Co-Authors: Mohammad Reza Khodabakhsh, Behzad NazariAbstract:IntroductionIt was about the late nineteenth century that assessment appeared as a domain of interest for researchers and educators, and the rife assessments were initiated only in the twentieth century (Gould, 1996).According to Gould (1996) in the 1900s when the USA started using Tests of general intelligence to evaluate immigrants and to evaluate the abilities of Army new members, standardized Testing became amazingly widespread. Subsequently, standardized Tests have been used in other contexts such as educational settings.Traditional summative assessment attempts to summarize students' learning at some point in time, say the end of a course, but it cannot provide the immediate, contextualized feedback useful for helping teacher and students during the learning process (Garb, 2008). So, the dynamic and holistic feature of assessment cannot be fully exploited.As a matter of fact, assessment is becoming a big challenge for those engaging in the field of teaching. Bailey described assessment as an information gathering activity. McNamara (2004, p.765) referred to gaining insights into learners' level of knowledge or ability as the purpose of assessment. In this way, learnt information via assessment is of high importance and considered a vital dimension of proper Instruction. It also equips us to get involved in the cornerstone terms of Dynamic Assessment, (henceforth, DA) "teaching to the Test," "narrowing of the curriculum," and "assessment-driven Instruction", which make this point clear that assessment and teaching are not separated from each other but they are, possibly, at odds with one another (Linn, 2000; Lynch, 2001; McNamara, 2001; Moss, 1996).Teachers' lack of acquaintance with principles and theories of practical assessment can also highlight the distinction between assessment and Instruction. Most of the time, teachers attend their classrooms unprepared to develop acceptable Testing instruments to monitor Testing term, and to analyze the outcomes (Torrance and Pryor, 1998), but they are supported with eclectic practical collection of Testing types far from the deep understanding of underlying theories .Teachers' mastery in assessing individuals is considered as the construct diagnostic competence ( Edelenbosgt and Kubanek-German , 2004). Based on their findings, they claim that teachers are not equally proficient in realizing the level of the students. The bifurcation between assessment and Instruction becomes clearer when considering the volume's title of Bachman and Cohen's (1998): Interfaces between Second Language Acquisition and Language Testing Research, focuses on the rising interaction between researchers in the concerning fields.Nowadays, one of the major and common methods of Testing in the world of second and foreign language learning is the product oriented one. Many language teachers around the world consider final assessment Tests a framework of their assessment. The cornerstone rationale behind Testing students after instructing them for a definite period of time is to observe how much of the Instruction the students have received on the subject. It is also worth mentioning that we frequently hear that a teacher acknowledges the drawbacks of any special assessment method which leads some talented students to attend weakly at the final Test, whereas, s/he performs well in the class. Applying Vygotsky's sociocultural theory in assessment, dynamic assessment in language learning might offer new insights to assessment in the language classroom.Assessment takes place not in isolation from Instruction but as an inseparable feature of it. Inseparably from each other, assessment and Instruction are integrated as a single activity. This pedagogical approach, known as Dynamic Assessment (DA), seeks to manage an Instruction-based assessment.The concept of DA does not speak of any specific way of Testing. Indeed, dynamic assessment is a whole different approach, or an umbrella term (Elliott, 2003), to the issue of Testing in the language classroom and this approach can be devoted to any way of Testing ranging from multiple choice to essay writing, and with a great variety of student backgrounds from monolingual environments to linguistic diversities (Haney and Evans, 1999; Laing and Kamhi, 2003). …
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teach to Test Instruction of dynamic assessment a critical overview
Bellaterra Journal of Teaching & Learning Language & Literature, 2012Co-Authors: Behzad NazariAbstract:The present article aims to meticulously focus on the integration of the assessment and Instruction which leads to a new approach, Dynamic Assessment, based on the principles of Socio-cultural Theory of Mind (SCT) developed by L. S. Vygotsky and his colleagues. A Vygotskian approach to language assessment suggests that the ‘process of development’ should be viewed as a predictor of the individual’s or the group’s future performance. Dynamic assessment has developed as an alternative to static types of assessment, i.e. standardized and/or non-dynamic assessment (SA/NDA). However, it is not regarded as a replacement for the other Test types, rather as a complement. The present paper is a modest attempt to provide an overview of the literature that set the groundwork for DA, as well as current research in the field of this type of assessment.
Ying Zhang - One of the best experts on this subject based on the ideXlab platform.
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Asian Test Symposium - Automatic Test Program Generation for Out-of-Order Superscalar Processors
2012 IEEE 21st Asian Test Symposium, 2012Co-Authors: Ying Zhang, Ahmed Rezine, Petru Eles, Zebo PengAbstract:This paper presents a high-level automatic Test Instruction generation (HATIG) technical that allows, for the first time, to Test the scheduling unit of an out-of-order super scalar processor. This technique leverages on existing bounded model checking tools in order to generate software-based self-Testing programs from a global EFSM model of the processor under Test. The experimental results have demonstrated the efficiency of the proposed technique.
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Automatic Test Program Generation for Out-of-Order Superscalar Processors
2012 IEEE 21st Asian Test Symposium, 2012Co-Authors: Ying Zhang, Ahmed Rezine, Petru Eles, Zebo PengAbstract:This paper presents a high-level automatic Test Instruction generation (HATIG) technical that allows, for the first time, to Test the scheduling unit of an out-of-order super scalar processor. This technique leverages on existing bounded model checking tools in order to generate software-based self-Testing programs from a global EFSM model of the processor under Test. The experimental results have demonstrated the efficiency of the proposed technique.
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Asian Test Symposium - Software-Based Self-Testing of Processors Using Expanded Instructions
2010 19th IEEE Asian Test Symposium, 2010Co-Authors: Ying Zhang, Huawei Li, Xiaowei LiAbstract:In this paper, an automatic Test Instruction generation (ATIG) technique using expanded Instructions is presented for software-based self-Testing (SBST) of processors. First, mappings between expanded Instructions and signals are obtained through data mining, and they are used to impose value ranges of expanded Instructions on component signals and generate Instruction-level constraints. Second, virtual circuits are established based on the Instruction-level constraints, and Test patterns are generated for the constrained components. Third, Test patterns are translated into Test Instructions according to the values of controlling signals and constraints for their mappings to Instructions, and an SBST program is produced after assembling the Test Instructions. Experimental results on the Parwan processor show that the proposed ATIG technique can achieve 94.8% stuck-at fault coverage, which is close to that of the full scan Test generation method. In addition, it can cut down 57% Test volume of the previous random pattern generation based SBST technique, while the Test time reduces to one thirteenth of the previous SBST technique.
H Esmaeilzadeh - One of the best experts on this subject based on the ideXlab platform.
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Test Instruction set tis for high level self Testing of cpu cores
Asian Test Symposium, 2004Co-Authors: Saeed Shamshiri, H Esmaeilzadeh, Z NavabiAbstract:TIS (Test Instruction set) is an Instruction level technique for CPU core self-Testing. This method is based on enhancing a CPU Instruction set with Test Instructions. TIS replaces the NOP Instruction that is available in most processors with Test Instructions so that online Testing can be done with no performance penalty. This method can be applied to both offline and online (concurrent) Testing of all types of processors (single-cycle, multi-cycle and pipelined). TIS is appropriate for pipelined architectures in which one or many NOP Instructions (or stalls) are inserted between Instructions that are data or control dependent. We have implemented this Test method on a pipelined CPU core and several Test programs for this pipelined CPU are used to illustrate the method. Also fault coverage results are presented to demonstrate the effectiveness of the TIS Test technique.
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Asian Test Symposium - Test Instruction set (TIS) for high level self-Testing of CPU cores
13th Asian Test Symposium, 2004Co-Authors: Saeed Shamshiri, H Esmaeilzadeh, Z NavabiAbstract:TIS (Test Instruction set) is an Instruction level technique for CPU core self-Testing. This method is based on enhancing a CPU Instruction set with Test Instructions. TIS replaces the NOP Instruction that is available in most processors with Test Instructions so that online Testing can be done with no performance penalty. This method can be applied to both offline and online (concurrent) Testing of all types of processors (single-cycle, multi-cycle and pipelined). TIS is appropriate for pipelined architectures in which one or many NOP Instructions (or stalls) are inserted between Instructions that are data or control dependent. We have implemented this Test method on a pipelined CPU core and several Test programs for this pipelined CPU are used to illustrate the method. Also fault coverage results are presented to demonstrate the effectiveness of the TIS Test technique.